Home: IP Portfolio > Verification IP > Simulation VIP > VIP for Ethernet 100GPL (802.3ck)

VIP for Ethernet 100GPL (802.3ck)

Incorporating the latest protocol updates, the mature and comprehensive Cadence® Verification IP (VIP) for the Ethernet 100GPL protocols provides a complete bus functional model (BFM), integrated automatic protocol checks, and coverage model. Designed for easy integration in testbenches at IP, system-on-chip (SoC), and system levels, the VIP for Ethernet 100GPL helps you reduce time to test, accelerate verification closure, and ensure end-product quality. The VIP for Ethernet 100GPL runs on all major simulators and supports SystemVerilog and e verification languages along with associated methodologies, including the Universal Verification Methodology (UVM) and Open Verification Methodology (OVM).

The VIP for Ethernet 100GPL enables verification of Ethernet interfaces in standalone, partial stack, and full stack mode for speeds from 10Mbps to 400Gbps:

  • XMII level, that is, between MAC and PHY
  • Between PHY sub-layers, that is, PCS, PMA, PMD
  • Between link partners, that is, TX Station and RX Station

The VIP for Ethernet 100GPL complies with IEEE 802.3ck Ethernet standards and draft specifications. It supports other widely popular Ethernet interfaces, which are proprietary and based on IEEE 802.3.

Specification Support

  • IEEE 802.3ck Draft 0.3
  • IEEE 802.3-2018

Key Features

Feature Name
Description

100GPL Features

100GPL interface supported on IEE802.3ck supports:

  • 100GKR1/100GCR1

  • 200GKR2/200GCR2

  • 400GKR4/400GCR4

  • Auto-negotiation supported for all PHY types

  • PMD link training supported

  • Single clock mode supported

  • Block lock FSM implemented

 

400Gbps Interfaces

400Gbps Ethernet interfaces based on IEEE 802.3bs

  • Supports 400GMII

  • Supports 400GBase-R PCS and PMA

  • Supports PMD interfaces

    • 400GBase-SR16

    • 400GBase-FR8/400GBase-LR8

    • 400GBase-DR4

  • Supports RS FEC

  • Supports Energy-Efficient Ethernet

200Gbps Interfaces

200Gbps Ethernet interfaces based on IEEE 802.3bs

  • Supports 200GMII

  • Supports 200GBase-R PCS and PMA

  • Supports PMD interfaces: 200GBase-DR4/200GBase-FR4/200GBase-LR4/200GBase-KR4/200GBase-CR4/200GBase-SR4

  • Supports RS FEC

  • Supports PMD training

  • Supports Energy-Efficient Ethernet

  • Supports LL FEC for 200GBASE-CR4 / KR4

100Gbps Interfaces

100Gbps Ethernet interfaces based on IEEE 802.3-2018

  • Supports CGMII

  • Supports 100GBase-R PCS and PMA

  • Supports PMD interfaces

    • 100GBase-CR10/100GBase–SR10

    • 100GBase-CR4/100GBase-KR4/100GBase-KP4

    • 100GBase-KR2/100GBase-CR2/100GBase-SR2

    • 100GBase-DR

  • Supports RS FEC

  • Supports fire-code FEC

  • Supports PMD training

  • Supports backplane auto-negotiation

  • Supports Energy-Efficient Ethernet

  • Supports LL FEC for 100GBASE-CR4 / KR4

50Gbps Interfaces

50Gbps Ethernet interfaces based on IEEE 802.3-2018 and 25/50 Gigabit Ethernet Consortium

  • Supports 50GMII

  • Supports 50Gbase-R PCS and PMA

  • Supports fire-code FEC

  • Supports RS FEC

  • Supports PMD interfaces: 50GBase-KR/50GBase-CR/50GBase-S

  • Supports back-plane auto-negotiation

  • Supports PAM4/NRZ lane encoding/decoding

  • Supports Energy-Efficient Ethernet

  • Supports LL FEC for 50GBASE-R

 

40Gbps Interfaces

40Gbps Ethernet interfaces based on IEEE 802.3-2018

  • Supports XLGMII

  • Supports 40Gbase-R PCS and PMA

  • Supports fire-code FEC

  • Supports PMD interfaces: 40GBase-KR4/40GBase-CR4/40GBase-SR4

  • Supports backplane auto-negotiation

  • Supports Energy-Efficient Ethernet

25Gbps Interfaces

25Gbps Ethernet interfaces based on IEEE 802.3by-2016 and 25 Gigabit Ethernet Consortium

  • Supports 25GMII

  • Supports 25GBase-R PCS and PMA

  • Supports fire-code FEC

  • Supports RS FEC

  • Supports PMD interfaces: 25GBase-CR/25GBase-KR

  • Supports back-plane auto-negotiation

  • Supports Energy-Efficient Ethernet

  • Block lock FSM implemented

 10Gbps Interfaces

 10Gbps Ethernet interfaces based on IEEE 802.3-2018

  • Supports XGMII

  • Supports 10GBase-R and XSBI PCS and PMA

  • Supports 10GBase-KR/10GBase-KX4

  • Supports XAUI

  • Supports RXAUI with 10/20/40bit per lane

  • Supports fire-code FEC for 10GBase-KR

  • Supports PMD training

  • Supports backplane auto-negotiation for 10GBase-KX4 and 10GBase-KR

  • Supports Energy-Efficient Ethernet

  • USXGMII interfaces: Single-Port and Multi-Port (with RS-FEC)

  • Supports PCH feature for USXGMII

  • Block lock FSM implemented

1Gbps Interfaces

1Gbps Ethernet interfaces based on IEEE 802.3-2018

  • Supports GMII

  • Supports 1000Base-KX

  • Supports TBI

  • Supports QSGMII Rev 1.2

  • Supports SGMII Rev 1.8

  • Supports USGMII

    • QSGMII

    • OSGMII

  • Supports RGMII

  • Supports clause 73 backplane auto-negotiation

  • Supports clause 37 auto-negotiation

  • Supports full duplex and half duplex of operation

  • Supports Energy-Efficient Ethernet

 10/100Mbps Interfaces

 10/100Mbps Ethernet interfaces based on IEEE 802.3-2018

  • Supports MII

  • Supports RMII

 Dynamic Switching

 Supports run-time speeed switching

 PMA Bus-Width

 Supports configurable PMA bus width:2, 4, 8, 10,16, 20, 32, 40, 64, 66, and 80 bits

 Clock, Jitter, Drift

 

  • Single Clock mode only for selected interfaces and speeds

  • Support for external clock mode

  • Supports CDR for serial interfaces

  • Support for internal clock mode for parallel bus-width interfaces

  • Jitter and skew support in internal clock mode

  • Auto-detection and correction of clock frequency drift in internal clock mode

Flow Control

Supports pause FC and PFC pause FC

Frames

Supports the following frame types:

  • Ethernet 802.3 (Type and Length defined)
  • Jumbo frame
  • MAGIC frame
  • Version II frame
  • Pause frame
  • PFC Pause frame
  • Management frame
  • Tagged Frame:
    • Single Tagged (Q-VLAN tag and S-VLAN tag)
    • Double tagged (S-VLAN tag and Q-VLAN tag)
  • Upper Layer Frames:
    • TCP
    • UDP
    • IPV4
    • IPV6
    • SNAP
    • MPLS
    • FC
    • MACSEC

 Custom Frame

 Proprietary header support

 MDIO Interface

 Supports MDIO interface as per Clause 22 and Clause 45

 Phy Timestamping

 Supported for 10GBaser and 25Baser interfaces

Key Verification Capabilities

  • SV coverage infrastructure for extendable coverage

  • Callback-based error injection capability for creation of illegal stimulus from the VIP

  • Predefined protocol checkers to verify the compliance of the MAC and PHY layers of the DUT model to protocol requirements

  • Monitor agent with analysis ports, which can be used for scoreboard purpose

  • Transaction tracker: Configurable tracking of all the transactions on the channels

Other Supported Features

Testbench language interfaces SystemVerilog and e
Methodology

UVM, up to version 1.2

OVM

Trace debug Yes
Functional coverage - SV  Yes
Dynamic activation Yes
RapidCheck Yes