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Five Emerging DRAM Interfaces You Should Know for your Next Design

Producing DRAM chips in commodity volumes and prices to meet the demands of the mobile market is no easy feat, and demands for increased bandwidth, low power consumption, and small footprint don’t help. This paper reviews and compares five next-generation DRAM technologies—LPDDR3, LPDDR4, Wide I/O 2, HBM, and HMC—that address these challenges.


Because dynamic random-access memory (DRAM) has become a commodity product, suppliers are challenged to continue producing these chips in increasingly high volumes while meeting extreme price sensitivities. It’s no easy feat, considering the ongoing demands for increased bandwidth, low power consumption, and small footprint from a variety of applications. This paper takes a look at five next-generation DRAM technologies that address these challenges.

Mobile Ramping Up DRAM Demands

Notebook and desktop PCs continue to be significant consumers of DRAM; however, the sheer volume of smartphones and tablets is driving rapid DRAM innovation for mobile platforms. The combined pressures of the wired and wireless world have led to development of new memory standards optimized for the differing applications. For example, rendering the graphics in a typical smartphone calls for a desired bandwidth of 15GB/s—a rate that a two-die Low-Power Double Data Rate 4 (LPDDR4) X32 memory subsystem meets efficiently. At the other end of the spectrum, a next-generation networking router can require as much bandwidth as 300GB/s—a rate for which a two-die Hybrid Memory Cube (HMC) subsystem is best suited.

LPDDR4 and HMC are just two of the industry’s emerging memory technologies. Also available (or scheduled for mass production in the next couple of years) are LPDDR3, Wide I/O 2, and High Bandwidth Memory (HBM). But why deal with all of these different technologies? Why not just increase the speed of the DRAM you are already using as your application requirements change?