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Cadence Receives Two Customers’ Choice Awards for Papers Presented at TSMC OIP Ecosystem Forum

SAN JOSE, Calif., 25 Nov 2013

Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, announced today that it received two Customers’ Choice Awards for papers at TSMC’s recent Open Innovation Platform® (OIP) Ecosystem Forum. One was titled, “Resistance, Pin Access and FinFET Parasitics,” and was developed by Paul Cunningham, Rachid Salik, Hitendra Divecha and Rahul Deokar. The other, titled, “16G Multi-Standard SerDes IP in TSMC’s 16nm FinFET Process,” was collaboratively authored by Eric Naviasky, Tom Wilson, Bob Salem and Jason Chen.

The awards were based on surveys completed by conference attendees. 

“Our customers appreciate and benefit from the work Cadence is doing to help them bring their 16nm FinFET designs to market,” said Suk Lee, TSMC Senior Director, Design Infrastructure Marketing Division. “These technical papers demonstrate enabled solutions through our close collaboration to help leading innovators embrace TSMC’s most advanced manufacturing processes.”

The papers can be viewed and downloaded on TSMC Online starting November 18, 2013. Cadence previously announced it received three TSMC Partner of the Year awards at this year’s OIP conference for work with the foundry on analog/mixed signal IP, 16nm FinFET design infrastructure, and 3D IC design solutions.

About Cadence

Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available here.

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