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Tensilica’s New GUI Helps Cut Chip Energy Consumption

SANTA CLARA , California, March 31, 2008 — Tensilica, Inc. today announced that it has added a new graphical user interface (GUI) to its popular Xenergy estimator, a unique energy estimator for both Xtensa configurable processors and Diamond Standard processors. This "first of its kind" tool allows software developers to evaluate trade-offs, so their software can be optimized for power, and lets hardware designers optimize the design of Xtensa configurable processors for total energy consumption.

"Today, total energy consumption is a primary design consideration for both hardware designers and software developers in most market segments," stated Steve Roddy, Tensilica’s vice president of marketing and business development. "Often, it isn’t intuitive which design decisions will have the biggest impact on overall energy consumption for a new SOC design. By using Xenergy, designers can quickly evaluate the trade-offs and know that they’ve picked the most energy efficient way to design new products."

Xenergy for Optimized Processor Hardware Configuration

Configurable processor technology has long been known for its potential to accelerate performance. But tailoring a processor to a given task can also be used with energy minimization as a key consideration. Using Xenergy, hardware designers can drive Xtensa processor configuration choices to dramatically lower the total clock processor cycles required to perform a given functional workload, thereby reducing total energy consumed. Designers pick from a menu of different configuration options and add custom processor extensions to try to reduce total core power consumption.

The Xenergy energy estimator calculates total energy consumption for a specific software workload on a candidate processor configuration. Comparisons between candidate processors is graphically displayed. Output can be a simple text file or a colorful graph for easy evaluation. Photos are available in the News section of www.tensilica.com.

Tests of processor configurations for common embedded processing kernels such as dot product, the Advanced Encryption Standard (AES) encryption, Viterbi decoding, and Fast Fourier Transform (FFT) show that the energy improvements from processor customization can range from 2x to 83x (all comparisons using common process, design flow and libraries).

Dot Product
Baseline Xtensa
K Cycles
Energy (µJ)
Optimized Xtensa
K Cycles
Energy (µJ)
Energy Improvement

The Xenergy estimator also can be used to evaluate the power savings potential of different process technologies, instruction and data cache sizes, RAM and ROM sizes, and many other Xtensa processor configuration options.

Xenergy for Optimized Software Design

Even after a processor configuration is chosen, or after an SOC has been fabricated, software developers can also use the Xenergy estimator to fine tune their C code to reduce energy dissipation by the processor and its memories. For example, a developer might use the feedback provided by the Xenergy tool to decide to restructure the allocation of data structures in local and main memories to reduce memory and bus accesses, which will lower overall energy expenditures. The Xenergy estimator gives the software developer fast, visual feedback and pinpoints the code hot spots that are consuming the most processor cycles and generating the most memory accesses.


Xenergy, with its new graphical user interface, is shipping now as part of Tensilica’s Software Development Kit, which includes all software development tools, the instruction set simulator, and the Xtensa Xplorer design environment.

About Tensilica

Tensilica offers the broadest line of controller, CPU and specialty audio and video DSP processors on the market today, in both an off-the-shelf format via the Diamond Standard Series cores and with full designer configurability with the Xtensa processor family. Tensilica's low-power, benchmark-proven processors have been designed into high-volume products at industry leaders in the digital consumer, networking and telecommunications markets. All Tensilica processor cores are complete with a matching software development tool environment, portfolio of system simulation models, and hardware implementation tool support. For more information on Tensilica's patented approach to the creation of application-specific building blocks for SOC design, visit www.tensilica.com.

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Editors’ Notes:

  • Tensilica and Xtensa are registered trademarks belonging to Tensilica Inc. All other company and product names mentioned are trademarks and/or registered trademarks of their respective owners.
  • Tensilica’s announced licensees include Afa Technologies, ALPS, Aquantia, Astute Networks, Atheros, AMD (ATI), Avision, Bay Microsystems, Berkeley Wireless Research Center, Broadcom, Brocade, Chiplen, Cisco Systems, CMC Microsystems, Conexant Systems, DS2, EE Solutions, Epson, ETRI, FUJIFILM Microdevices, Fujitsu Ltd., Hudson Soft, iBiquity Digital, Ikanos Communications, Intel, Juniper Networks, LG Electronics, Lucid Information Technology, Marvell, MediaPhy, NEC Laboratories America, NEC Corporation, NetEffect, Neterion, Nethra Imaging, Nippon Telephone and Telegraph (NTT), NuFront, NVIDIA, Olympus Optical Co. Ltd., Penstar, Plato Networks, PnpNetwork Technologies, Samsung, Sandforce, Server Engines, SiBEAM, Silicon Optix, Sony, STMicroelectronics, Stretch, TranSwitch Corporation, u-Nav Microelectronics, UpZide, Valens Semiconductor, Validity Sensors, Victor Company of Japan (JVC), WiLinx, and XM Radio.