Home > News & Events > Press Releases > June 19, 2007

Tensilica Enhances Reference Flow With Cadence Encounter RTL Compiler

Cadence Technologies Reduce Area and Power And Ensure Quality Implementation for Tensilica Embedded Cores

SAN JOSE and SANTA CLARA, Calif. - June 19, 2007 -- Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic-design innovation, and Tensilica, Inc., a leading IP supplier of high-efficiency standard and extensible processor cores, today announced that Tensilica incorporated Cadence Encounter RTL Compiler with global synthesis in its CAD flow which supports both Diamond and Xtensa cores. Encounter RTL Compiler with global synthesis enables Tensilica customers to achieve smaller, faster and lower-power implementations for microprocessor designs using Tensilica IP.

Tensilica, a member of the Cadence OpenChoice IP program, used a top-down methodology featuring its market-leading processor IP in conjunction with Encounter RTL Compiler, which performs multi-objective synthesis to create designs optimized for timing, area, and power.

Tensilica is a leading IP supplier in mobile multimedia (audio and video) and offers the broadest line of processor cores in the market today in both an off-the-shelf format via the Diamond Standard Series cores and with full designer configurability with the Xtensa processor family. All Tensilica processor cores are complete with a matching software development tool environment

"We are excited to enable our customers with synthesis solutions from Cadence," said Chris Rowen, president and CEO at Tensilica. "What impressed us most about Encounter RTL Compiler is that it was easy to set up and use. Tensilica customers using the Encounter technology now have access to an optimal synthesis solution that provides excellent power-versus-area tradeoffs for SoC (system-on-chip) design."

With the RTL Compiler multi-objective optimization, customers can achieve significant advantages in area, speed and performance. In tests, Tensilica achieved a 10 percent increase in speed and a reduction of cell area of 5 percent. The RTL Compiler global synthesis solution improves performance, reduces die sizes, lowers power consumption, and speeds up design closure through place and route.

"Encounter RTL Compiler plays a significant role in enabling our IP partners to improve their quality of silicon in a very competitive market," said Jan Willis, senior vice president, Industry Alliances at Cadence. "We are delighted to collaborate with Tensilica to jointly enable our customers for better quality, performance, and power consumption in their designs."

RTL Compiler with global synthesis is available in XL and GXL offerings to meet customers’ design and cost objectives. This key technology is part of the Cadence Encounter digital IC design platform and a component of the Cadence Logic Design Team Solution.

About Cadence

Cadence enables global electronic-design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. Cadence reported 2006 revenues of approximately $1.5 billion, and has approximately 5,200 employees. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com

About Tensilica

Tensilica offers the broadest line of controller, CPU and specialty DSP processors on the market today, in both an off-the-shelf format via the Diamond Standard Series cores and with full designer configurability with the Xtensa processor family. Tensilica’s low-power, benchmark proven processors have been designed into high-volume products at industry leaders in the digital consumer, networking and telecommunications markets. All Tensilica processor cores are complete with a matching software development tool environment, portfolio of system simulation models, and hardware implementation tool support. For more information on Tensilica's patented approach to the creation of application-specific building blocks for SOC design, visit www.tensilica.com

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Editors’ Notes:

  • Tensilica and Xtensa are registered trademarks belonging to Tensilica, Inc. Cadence and Encounter are registered trademarks, and the Cadence logo is a trademark of Cadence Design Systems, Inc. All other company and product names are trademarks and/or registered trademarks of their respective owners.
  • Tensilica’s announced licensees include Afa Technologies, ALPS, AMCC (JNI Corporation), Aquantia, Astute Networks, Atheros, ATI (AMD), Avago Technologies, Avision, Bay Microsystems, Berkeley Wireless Research Center, Broadcom, Cisco Systems, CMC Microsystems, Conexant Systems, Cypress, Crimson Microsystems, Design Art Networks, Enuclia, ETRI, EE Solutions, FUJIFILM Microdevices, Fujitsu Ltd., Hudson Soft, Hughes Network Systems, iBiquity Digital, Ikanos Communications, LG Electronics, Lucid Information Technology, Marvell, MediaWorks, NEC Laboratories America, NEC Corporation, NetEffect, Neterion, Nethra Imaging, Nippon Telephone and Telegraph (NTT), NuFront, NVIDIA, Olympus Optical Co. Ltd., Penstar, Plato Networks, PnpNetwork Technologies, sci-worx, Seiko Epson, Solid State Systems, Sony, STMicroelectronics, Stretch, TranSwitch Corporation, u-Nav Microelectronics, Victor Company of Japan (JVC), WiQuest Communications, and XM Radio.