Home > News & Events > Press Releases > February 20, 2006

Tensilica Offers Low Cost Development Tools for Diamond Standard Processors

Tools Help Designers Develop Chips with Significantly More Compact Code for Cost-Sensitive Electronic Systems

SANTA CLARA, CA – February 20, 2006 –Tensilica, Inc. today introduced a comprehensive software development kit for its Diamond Standard Series processors, a line of off-the-shelf synthesizable CPUs and DSPs (digital signal processors) ready for integration into SOCs (system-on-chip). Priced at just $1,000 for a node-locked license, these tools provide a comprehensive software development kit based on Tensilica’s Xtensa Xplorer development environment, which includes an Eclipse-based GUI (graphical user interface). A key component of the tools suite is Tensilica’s advanced C/C++ compiler (XCC). Tensilica’s XCC compiler uses aggressive optimization techniques to generate extremely compact code, enabling lower on- and off-chip memory requirements for cost-sensitive electronic systems.

"The comprehensive nature of our tool set allows designers to quickly generate compact, high-performance, production quality code for any or all of our Diamond Standard processors," stated Steve Roddy, Tensilica’s vice president of marketing. "The tool set also includes a pipeline-accurate instruction set simulator for all six Diamond Standard processors, which enables rapid development of application code."

Tensilica’s comprehensive tool set for the Diamond Standard processors includes:

  • Xtensa Xplorer - Diamond Edition integrated design environment (IDE) with performance evaluation tools
  • Pipeline-accurate instruction set simulator (ISS)
  • Tensilica’s Xtensa C/C++ Compiler (XCC)
  • Complete GNU-based toolchain (assembler, debugger, profiler, linker)
  • Optimized C libraries for all Diamond Standard cores

Xplorer IDE

The Xplorer IDE serves as a cockpit for SOC design with Diamond Standard processors. The Xplorer IDE provides a unified environment for C/C++ application software development, code profiling and debugging. It is a visual environment with a host of automation tools that enables rapid code development for complex SOC designs.

Instruction Set Simulator

Tensilica provides a clock-cycle-accurate, pipeline-modeled ISS matched to each of the Diamond Standard processors. The ISS is fast and accurate, with speeds two or more orders of magnitude faster than RTL (register transfer level) hardware simulation. By accelerating system simulation, Tensilica’s ISS decreases overall SOC design time.

C/C++ Compiler

The XCC Compiler for Diamond Standard processors is an advanced optimizing compiler that provides superior execution performance and smaller size of the compiled code. It provides feedback-directed compilation using profile data collected from the ISS or a target hardware system. The XCC Compiler also provides automatic vectorization for the Diamond Standard 545CK and automatic bundling of operations in VLIW bundles for the Diamond Standard 570T, 545CK and 330HiFi.

Complete GNU-based Toolchain

Tensilica provides a complete GNU-based toolchain with an assembler, debugger, profiler and linker. The GNU software development tools are extremely robust and interface seamlessly with Tensilica’s advanced compiler code-generation capabilities.

Pricing and Availability

Tensilica’s tools for the Diamond Standard processors start at $1,000 per year for a single-seat node-clocked license and $2,000 per year for a floating seat license. The tools are available now.

About Tensilica

Tensilica offers the broadest line of controller, CPU and specialty DSP processors on the market today, in both an off-the-shelf format via the Diamond Standard Series cores and with full designer configurability with the Xtensa processor family. Tensilica’s low-power, benchmark proven processors have been designed into high-volume products at industry leaders in the digital consumer, networking and telecommunications markets. All Tensilica processor cores are complete with a matching software development tool environment, portfolio of system simulation models, and hardware implementation tool support. For more information on Tensilica's patented approach to the creation of application-specific building blocks for SOC design, visit www.tensilica.com.

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Editors’ Notes:

  • Tensilica and Xtensa are registered trademarks belonging to Tensilica Inc. All other company and product names are trademarks and/or registered trademarks of their respective owners.
  • Tensilica’s announced licensees include Agilent, ALPS, AMCC (JNI Corporation), Astute Networks, Atheros, ATI, Avision, Bay Microsystems, Berkeley Wireless Research Center, Broadcom, Cisco Systems, Conexant Systems, Cypress, Crimson Microsystems, ETRI, FUJIFILM Microdevices, Fujitsu Ltd., Hudson Soft, Hughes Network Systems, Ikanos Communications, LG Electronics, Marvell, MediaWorks, NEC Laboratories America, NEC Corporation, NetEffect, Neterion, Nippon Telephone and Telegraph (NTT), NVIDIA, Olympus Optical Co. Ltd., sci-worx, Seiko Epson, Solid State Systems, Sony, STMicroelectronics, Stretch, TranSwitch Corporation, u-Nav Microelectronics, and Victor Company of Japan (JVC).