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Designing SOCs with Configured Cores

Designing SOCs with Configured Cores

Unleashing the Tensilica Xtensa and Diamond Cores

By Steve Leibson

Published by Elsevier
ISBN: 0123724988; Published: July 11, 2006;
Copyright 2006;
Dimensions 7-1/2 x 9-1/4 ; Pages: 344; Edition: 1st.

Designing SOCs with Configured Cores

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In the 21st century, SOC design styles are changing. Not because they can but because they must. Moore's law and the side benefits of classical semiconductor scaling (faster transistors running at lower power at each new processing node) parted company when the semiconductor industry hit the 130 nm processing node just after the turn of the century. As a result, on-chip clock rates stopped falling as quickly as they had. On-chip clock rate and power dissipation have tracked Moore's law for nearly 30 years. But no longer.

The net effect of this split between Moore's law and classical scaling is to remove two of SOC design's key assumptions:

  • The next processing node promises faster processors.
  • Lower energy consumption for increasingly complex systems is just one processing node away.

As a result, SOC designers must become more sophisticated.

This book advocates a departure from decades-old design styles, although not as radical a departure as others may promote. System block diagrams need not change substantially to take full advantage of the resources available to SOC designers in the 21st century. However, many more blocks in these existing block diagrams can now be implemented with processors rather than hand-designed, custom-built logic blocks.

The result of this change alone will bring large benefits to system design. Blocks that were previously hard wired can now become firmware-programmable, which reduces design risk by allowing the SOC's function to change without the need to re-spin the chip.

In addition to advocating a shift to multiple processor SOC design, this book also promotes the idea that the almost universal use of globally shared buses should be substantially reduced. Buses are shared resources and came into existence in the 1970s to accommodate the pin limitations of packaged microprocessors. Such limitations don't exist on an SOC and these no-longer-in-effect limitations should therefore cease to hobble system architects. New, more efficient ways of interconnecting on-chip blocks exist and they should be used to improve system performance and reduce power dissipation.

None of these changes should cause experienced system designers any headaches. All of the concepts advocated in this book should be familiar to any system designer. The suggested departure from conventional design is more a shift in perspective that favors one type of existing design style (processor-based block implementation) over another (custom-designed logic). The means to achieving this shift is through the use of configurable and pre-configured processor cores that provide substantially better (orders of magnitude) system performance than widely used, general-purpose processor cores.