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Hardware/Software Design Flow

Tensilica Processors Accelerate Time to Market

No matter what hardware or software design flow you like to use, Cadence® Tensilica® processors will seamlessly plug into it. And we will help you get your design done faster because Tensilica's processors are much easier to design and customize than any other processors and comparable RTL blocks.

Whether it be plugging into your existing software development or EDA flows, or streamlining the verification process for creation of a complex SoC block, Tensilica processors accelerate your time to market.

Let's take a look at the steps you might take in your design flow:

Hardware/Software Flow

Tensilica processors fit into standard hardware and software design flows

Start with MATLAB

Are you using MATLAB to figure out the best algorithm for your design? You can use your MATLAB output in your Tensilica flow. Our customer knowledge base includes application notes on how to link MATLAB and our ISS as well as how to emulate TIE functions in MATLAB.

System Exploration and Modeling

The earliest phases of any SoC design are the system analysis, exploration, and modeling phases. We provide unparalleled support for a variety of system modeling strategies.

For architects doing C-level simulations, the Tensilica Xtensa® Instruction Set Simulator (ISS) is a fast and accurate C model of the Xtensa processor. The Xtensa Modeling Protocol (XTMP) is a C-callable executable version of the ISS program that can be, and has been successfully, integrated into larger SoC or system simulation environments.

For architects interested in SystemC simulation, XTensa SystemC performs functions similar to XTMP and has been successfully integrated into all of the SystemC platforms from the leading EDA companies.

World-Class EDA Flow Support

The Xtensa Processor Generator creates a fully synthesizable, 100% digital RTL description that is compatible with any hardware EDA design flow. In addition, the Xtensa Processor Generator provides modeling and EDA tool support custom tailored to your exact configuration. We support the leading tools from all the major EDA vendors. Contact your sales representative or support engineer for information about the current tool versions supported.


Pre-verified cores

All Xtensa processor cores are pre-verified before they are delivered to you from the Xtensa processor generator, so you can avoid the lengthy verification process required by hand-crafted RTL blocks. For more information on the overall processor verification process, read "How Tensilica Verifies Processor Cores."


We use System Verilog to implement monitors on all processor interfaces. These monitors facilitate integration of the Xtensa RTL source code into your design and your system testbench. The monitors included with each DSP check for protocol violations of the hardware attached to the Xtensa processor and provide trace and PC monitoring capabilities.

Foolproof Custom Instructions

Concerned that optimizing a core may cost you a lot of verification effort? Not true! All designer-defined TIE instructions are correct-by-construction using Tensilica’s patented processor generation technology. What you specify in the single-source TIE description is what will be implemented automatically, correctly, and consistently in hardware, software tools, and models.

You do not have to re-verify the Tensilica core. Your optimizations are performed using our automated generator, which verifies the core for you. This is why we can claim the cores you generate are correct by construction. Since you never make manual changes to the core, there's no need to verify anything other than that your design intent is true and that it works the way you intended in your system.

To further assure that what you specified is what you intended to create, the Xtensa Processor Generator automatically creates a self-checking testbench for each processor that incorporates the ISS and the processor hardware RTL. This testbench enables you to run and verify your testbench C code on the real hardware description to fully exercise your designer-defined TIE instructions and ensure that your specification of the TIE instruction meets your system requirements.