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Handling The Hard Data Processing Tasks in SoCs

Handling the Difficult Tasks in Data Processing

Spotlight Video

Chris Rowen discusses the benefits of data processing with SemIsrael.

Designers have long understood how to use a single processor for the control functions in an SoC design. However, there are a lot of data-intensive functions that control processors cannot handle. That's why designers design RTL blocks for these functions. However, RTL blocks take a long time to design and verify, and are not programmable to handle multiple standards or changes.

Designers often want to use programmable functions in the dataplane, and only Cadence offers the core technology that overcomes the top four objections to using processors for data processing:

  1. Data throughput—All other processor cores use bus interfaces to transfer data. Cadence® Tensilica® cores allow designers to bypass the main bus entirely, directly flowing data into and out of the execution units of the processor using a FIFO-like process, just like a block of RTL.
  2. Fit into hardware design flowWe are the only processor core company that provides glueless pin-level co-simulation of the instruction set simulator (ISS) with Verilog simulators from Cadence, Synopysys, and Mentor. Using existing tools, designers can simulate the processor in the context of the entire chip. And we offer a better verification infrastructure over RTL, with pre-verified state machines.
  3. Processing speedOur patented automated tools help the designer customize the processor for the application, such as video, audio, or communications. This lets designers use Tensilica DSPs to get 10 to 100 times the processing speed of traditional processors and DSP cores.
  4. Customization challengesMost designers are not processor experts, and are hesitant to customize a processor architecture for their needs. With our automated processor generator, designers can quickly and safely get the customized processor for their exact configuration.

The Best of CPUs and DSPs with Better Performance

Tensilica processors combine the best of CPUs and DSP cores with much better performance and fit for each application. Where our processors really shine is in the dataplane - doing the hard work, handling complex algorithms, and offloading the host processor.  Our processors and DSPs deliver programability, low power, optimized performance, and small core size. 

dataplane processors

Lower Design Risk than RTL

The inherent programability in the Tensilica processor enables performance tuning and bug fixes via firmware upgrade, lowering design risk and allowing faster time to market. Our technology pre-verifies all changes made to the processor, and guarantees that your processor design will be correct by construction. You don't actually have to get in there and make the processor changes yourself—our automated tools will take your guidance and make the changes for you, correctly.

Fundamentally Different from Standard CPUs and DSPs

Here are the fundamental differences between our processors and traditional processors and DSP cores:

Traditional Processors and DSPsTENSILICA PROCESSORS AND DSPs
Processors and DSPs are fixed function, generic, non-optimized Customizable processors provide a unique combination of optimized processor plus DSP
Changing or designing a processor is expensive, difficult and risky. Requires a team of 50+ processor designers. Fully automated processor and software tools creation. One algorithm expert or SoC designer can create a customized core in less than one hour.
Processors and DSPs offer limited power and performance Our processors typically outperform traditional DSP cores and CPUs by 10X or more in power and performance
I/O bottlenecks render processors and DSP cores inappropriate for dataplane processing and are difficult to integrate with RTL Our processors have unlimited user defined I/Os, mimicking RTL-style hardware dataflows for easy RTL integration
No differentiation: same hardware and in many cases software Reduce design risk while capturing proprietary knowledge into a customized implementation

Automated Creation of a Data Processing DSP and its Software Toolkit in Less than 1 Hour

We have automated much of the risk out of creating a customized processor. Using our tools, designers can create a customized core and matching software tools in less than an hour.

Automated hw/sw generation

Our automated process for creating customized dataplane processors

Find out more about how to customize our processors in our Product section.

Direct I/O Into and Out of the Processor

All other processor cores and DSP cores use bus interfaces to transfer data. Cadence's Tensilica processors allow designers to bypass the main bus entirely, directly flowing data into and out of the execution units of the processor using a FIFO-like process. We provide three ways of directly communicating, much like an RTL block. You can use our TIE Queues for FIFO connections, our TIE Ports for GPIO-like connections, and TIE Lookup interfaces for fast, easy connections to memories.