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VIP for USB4

The Cadence® Verification IP (VIP) for USB4 provides a highly capable verification solution for the USB4 protocol incorporating bus functional model (BFM) and integrated protocol checkers and coverage. It is based on the next-generation USB protocol architecture of USB4 specification. The VIP for USB4 enables multiple simultaneous data and display protocols and supports them to share the bandwidth over the bus. It supports the two-lane operation and up to 40Gbps speed.

Specification Support

The VIP is compliant with USB4 Specification Version 1.0.

Protocol Features

List of key features from the spec and as well other VIP capabilities supported are mentioned in the table below:


Logical Layer

  • Side Band Channel

  • Logical Layer State Machine

  • Both GEN2 and GEN3 speeds

  • Reed-Solomon forward error-correction code (RS-FEC)

  • Dual-Lane Skew

  • Low Power states

  • Sleep and wake

  • Error Cases and Recovery

  • Interoperability with Thunderbolt 3 (TBT3) compatibility

Transport Layer

  • Transport Layer Packets

  • Routing

  • Quality of Service (QOS)

    • Flow control schemes

    • Bandwidth arbitration and priority

  • Path Setup and Path Tear-Down

Configuration Layer

  • Router States

  • Control Packet Protocol

  • Router Enumeration

  • Hot Plug and Hot Unplug Events

Time Synchronization

  • Intra-Domain and Inter-Domain time sync

  • Bi-Directional and Uni-Directional state machines

  • Serial Time Link Protocol

Configuration Spaces

  • Support to read and write the defined configuration space

    • Router configuration space

    • Adapter configuration space

    • Path configuration space

  • Support to backdoor access the configuration space

USB3 Tunneling

  • USB3 Adapter Layer Encapsulation

  • Path Setup and Tear-Down

  • Isochronous Timestamp Mechanism

DP Tunneling

  • LTTPR and Non-LTTPR mode

  • DP-IN and DP-OUT Adapters

  • DP Adapter States

  • System Flows

  • AUX Request and Response Handling

  • DP Link Clock Sync

  • SST Tunneling

  • FEC

  • HDCP

PCIe® Tunneling

  • PCIe Adapter Layer Encapsulation

  • Path Setup and Tear-Down

  • Precision Time Management (PTM) Mechanism


  • Side Band Channel

  • Retimer Channel State Machine

  • Low Power

  • Clock Switching

  • Interoperability with Thunderbolt 3 (TBT3) compatibility 

Key Verification Capabilities

  • Capability to bypass spec features such as:

    • Bypass Side Band Channel

    • Bypass Enumeration

    • Bypass High Speed Link Training

  • Callback capabilities are powerful, use callbacks to:

    • Change or corrupt the packet fields, or delay a packet to create time-out scenarios, and so on

    • Collect coverage

    • Create scoreboard

  • Support to insert User Defined Packets at all major layers

  • SV coverage infrastructure for extendable coverage

  • Support for Pseudo Port to mimic adapter ports

  • Predefined protocol checkers to verify the DUT against the protocol requirements like HEC, IPG, Non-Rsvd, etc.

  • Monitor agent with analysis ports, which can be used for scoreboarding purpose

  • Register interface flow to change timing parameters to reduce simulation time

Other Supported Features

Simulator support

Xcelium™, VCS, and MTI

Testbench Language Interface



Universal Verification Methodology (UVM)

Trace debug


Functional coverage - SystemVerilog