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VIP for USB Type-C

This Cadence® Verification IP (VIP) for USB Type-C is a complete VIP solution for the Universal Serial Bus Type-C Cable and Connector Specification, Revision 1.3, 14 July 2017 and Universal Serial Bus Power Delivery Specification, Revision 3.0, V1.1. 12 Jan 2017.

The VIP for USB Type-C provides a mature, highly capable compliance verification solution that supports simulation and formal analysis making it applicable to intellectual property (IP), system-on-chip (SoC), and system-level verification. It provides full timing and bus functional modeling of USB Type-C and Power Delivery (PD).

This VIP provides support for USB Type-C Receptacles and Plugs. As Plug, it can be configured to have none/1/2 cable plugs embedded.

The VIP for USB Type-C is compatible with all main verification languages (such as Verilog, SystemVerilog, e, and VHDL) and industry-standard methodologies (such as UVM, OVM, and VMM), and runs on all leading simulators.

Specification Support

The base specifications for the USB Type-C and Power Delivery protocol are available at  http://www.usb.org/developers/docs.

Key Features

Key features from the specification that are implemented in the VIP are listed in the table below.

FEATURE NAME

DESCRIPTION

Receptacle and Plug Interfaces

Receptacle interface with support for port partner, Plug interface with support for SOP'/SOP"/none (has 1/2/0 cablePlugs), Receptacle detection of Plug orientation.

Type-C Configuration

Supports Type-C with Host (DFP)/Device (UFP) configuration, Type-C with DFP as source configuration, Type-C with UFP as Sink configuration.

Supports Type-C with DFP as DRP (Source/Sink) configuration, Type-C with UFP as DRP (Source/Sink) configuration.

Type-C Attach and Detach Detection Presently supports the detection.
Type-C Analog Signaling Presently supports signals interfaces: Analog signaling using SV Nettype, strength modeling, and digital signals.

Type-C Debug Accessory Mode

Supports Debug Accessory Mode
Biphase Mark Coding (BMC) Supports Biphase Mark Coding (BMC) over CC.
4b5b Encoding

Encodes 4-bit data to 5-bit symbols for transmission and decodes 5-bit symbols to 4-bit data for consumption by the receiver.

Ordered-Sets

Supports the physical layer ordered sets such as SOP, SOP', SOP", Hard Reset, Cable Reset, SOP'_Debug, and SOP"_Debug.

Physical Layer Physical layer data flow, signaling scheme, bit rate drift, trailing edge, idle detection, clock recovery, and lock onto the packet preamble.
Control Message

Supports control messages including GoodCRC, GotoMin, Accept, Reject, Ping, PS_RDY, Get_Source_Cap, Get_Sink_Cap, DR_Swap, PR_Swap, VCONN_Swap, Wait, Soft_Reset, Not_Supported, Get_Source_Cap_Extended, Get_Status, FR_Swap, Get_PPS_Status, and Get_Country_Codes.

Data Message Supports data messages including Source_Capabilities, Sink_Capabilities, Request, Battery_Status, Alert, and Get_Country_Info.
Extended Message Supports extended messages including Source_Capabilities_Extended, Status, Get_Battery_Cap, Get_Battery_Status, Battery_Capability, Get_Manufacturer_Info, Manufacturer_Info, Security, Firmware_Update, PPS_Status, Country_Codes, and Country_Info.
Vendor-Defined Message Supports vendor-defined messages such as Discover Identity, Discovery SVIDs, Discover Modes, Enter Mode, Exit Mode, and Attention.
Protocol Layer Message transmission and reception, state behaviors, use of timers, error handling, and AMS collision avoidance.
Policy Engine Source/Sink Port State Machine
Hard Reset Supports Hard Reset operation
Soft Reset Supports Soft Reset operation
Cable Reset Supports Cable Reset operation
Source Discovery of CablePlug Supports Source discovery of CablePlug
Built-In Self-Test (BIST)

Supports BIST Carrier Mode 2 and BIST Test Data

VCONN Swap Supports VCONN Swap operation
Power Role Swap Supports Power Role Swap operation
Data Role Swap Supports Data Role Swap operation
Fast Role Swap Supports Fast Role Swap operation
Integration of USB Communication Supports configuration and traffic for USB versions 2.0, 3.0, and 3.1
Support DisplayPort 2 Lane as AlternativeMode Supports DisplayPort 2 Lane + USB3.0 operations, bypass entry to DisplayPort alternate mode, and automatic entry into DisplayPort alternate mode
Support DisplayPort 4 Lane as AlternativeMode Supports DisplayPort 4 lane operations, bypass entry to DisplayPort alternate mode, and automatic entry into DisplayPort alternate mode

 

Key Verification Capabilities

  • Compliance: Contains hundreds of protocol checks to verify that the DUT adheres to the protocol rules defined in the USB Type-C and PD Specification
  • Predefined error injections such as Crc, 4b5b, PreamblePattern, PreambleBmc, Bmc for PD OrderedSets and Messages, and discarding a packet
  • Powerful callback capabilities:
    • To change or corrupt the packet fields or delay a packet to create time out scenarios
    • To collect coverage
    • To scoreboard
  • Configuration is dynamic using SOMA or UVM Config:
    • To change timing parameters to reduce simulation time
    • To control the functionality, such as changing power supply objects
  • Interface choice: serial (using svNetType for CC pin)
  • Register interface: 
    • To change the severity (Fatal, Error, Warning, Info) of protocol assertions
    • To control the functionality such as directing state transitions, RDO's content
    • To store VIP model information such as power role, data role, policy engine states, protocol transmission/reception/hard-reset states, which are easily accessible to the testbench
  • Traffic: 
    • Generates all PD transactions such as OrderedSets and Data/Control Messages
    • Responds to PD transactions

 

Other Supported Features

Assertion Coverage

Yes

Methodology Support

Complies with the Universal Verification Methodology (UVM)

Platform Support

Operates in both simulated and accelerated platforms for ultimate flexibility

Simulator Support

IES, VCS, MTI

Testbench Language Interfaces

Verilog, SystemVerilog, VHDL, NTB, e

Trace Debug Yes
UVM Agent Yes
Functional Coverage Yes
RapidCheck Yes
TripleCheck Yes
Transaction Log Yes

 

Supported Design-Under-Test Configurations 

Host Device Hub/Switch
Full Stack Controller Only PHY Only

 

Test Suite Options

Basic CMS PureSuite TripleCheck

Training