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VIP for USB 3.2

 

The Cadence® Verification IP (VIP) for USB is a complete VIP solution for the Universal Serial Bus Revision 3.2 Specification and errata. It provides a mature, highly capable compliance verification solution that supports simulation, formal analysis, and hardware acceleration platforms, making it applicable to intellectual property (IP), system-on-chip (SoC), and system-level verification. It provides full timing and bus functional modeling of USB.

The VIP for USB provides support for USB Hosts or Devices. It supports both super-speed-plus and super-speed modes and provides backward compatibility with USB 3.1, USB 3.0, and USB 2.0 as per the specifications. Currently, the VIP for USB provides a serial signaling interface to test and monitor all possible configurations of USB devices.

The VIP for USB is compatible with all main verification languages (such as Verilog, SystemVerilog, and e) and industry-standard methodologies (such as UVM, OVM, and VMM), and runs on all leading simulators.

Specification

The specification for USB 2.0, 3.0, 3.1, and 3.2 are available at http://www.usb.org/developers/docs.

Key Features

List the key features from the spec that are implemented in the VIP. List the important ones in the table below.

Feature Name
Description

Backward Compatibility

Supports USB3.2 and backward compatibility for USB3.1, USB3.0, USB 2.0, and USB1.1

Configurations

Supports Gen2x2, Gen1x2, Gen2x1, and Gen1x1

Physical Layer

  • Supports separate source clock per lane
  • Supports Gen1x2 8b10b encoding/decoding per lane
  • Supports Gen2x2 128b132b block encoding/decoding per lane
  • Supports LFSR per lane and enable/disable scrambling
  • Supports OS transmitted/received simultaneously on each negotiated lane
  • Supports Data Striping
  • Supports Gen2x2 Block Header Error with or without association
  • Supports Lane-Lane De-skew on RX
Link Layer
  • Supports LFPS, LBPM, and SCD only on configuration lane
  • LTSSM support for Receiver detection only on configuration lane
  • Supports for Ux Exit on configuration lane
  • LTSSM updates for eSS.Inactive, Rx.Detect, and Polling
  • LTSSM updates for U0, U1, U2, and U3
  • LTSSM updates for Recovery and Hot Reset
  • Increases the number of credits available from 4 to 7 for Gen2x2
Framework and Protocol Layer Updates value of Endpoint Companion and Isochronous Endpoint Companion descriptor type
Re-Timer
  • Supports re-timer presence announcement in Host and Device VIP
  • Supports re-timer SKP number calculation in Host and Device VIP
All Transaction Types

Supports all types of transfers: bulk, control, interrupt, and isochronous and split transactions

Loopback and BERT Supports PHY loop-back state with bit error rate test
OTG Support Supports OTG 1.3, 2.0, and 3.0 revisions with both A-device and B-device configurations
OTG Protocols Supports SRP (Session Request Protocol), ADP (Attach Detection Protocol), HNP (Host Negotiation Protocol), and RSP (Role Swapping Protocol)
Hub Supports hub training, basic topology enumeration, packet routing, and forwarding

 

Key Verification Capabilities

  • Compliance: Contains hundreds of protocol checks to verify that the DUT adheres to the protocol rules defined in the USB 3.2 Specification
  • Predefined error injections such as Crc5, Crc16, and Crc32 for header packets, link commands, data packets, discarding a packet, and so on
  • Callback capabilities are powerful; use callbacks to:
    • Change or corrupt the packet fields, or delay a packet to create time-out scenarios, and so on
    • Collect coverage
    • Scoreboard
  • Configuration is dynamic using SOMA or UVM configuration
    • Change timing parameters to reduce simulation time
    • Control the functionality, such as changing the end-point configuration, polarity inversion, number of ordered sets to transmit/receive, and so on
  • Enumeration: Capability to bypass the enumeration process, to do manual enumeration, or to enable auto enumeration process from the host VIP
  • Interface choice based on specification version:
    • Serial
    • DPDM
    • HSIC
    • UTMI/UTMI+:  MAC or MACRO (include-PHY) with 8 or 16-bit data width
    • ULPI: MAC or MACRO
    • PIPE: MAC, PHY, or MACRO (include-PHY) with 8, 16, or 32-bit PIPE width
  • Register interface: 
    • To change the severity (Error, Warning, Info) of protocol assertions
    • To initiate low-power enter/exit sequences from the VIP
    • To control the functionality, such as end-point buffers, to exercise device flow control, streaming
    • To store VIP model information, such as device states, device address, end-point information, LTSSM states, and so on, which is easily accessible by the testbench
  • Traffic:
    • Generates all USB transactions as a host, like initiating bulk (including streaming), control, isochronous, and interrupt transfers
    • Responds to USB transactions as a device
    • LMP header packets
    • Full control on the device VIP to do flow control like sending NRDY or ERDY

Other Supported Features

Testbench Language Interfaces

Verilog, SystemVerilog, e

UVM Agent

Yes

Functional Coverage -

SystemVerilog e

Dynamic Activation Yes

TripleCheck

Yes 

RapidCheck

 

Yes