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VIP for USB 3.2

The Cadence® Verification IP (VIP) for USB 3.2 is a complete VIP solution for the Universal Serial Bus Revision 3.2 Specification and erratas. It provides a mature, highly capable verification solution for RTL simulation, making it applicable to intellectual property (IP), system-on-chip (SoC), and system-level verification. It provides full timing and bus functional modeling of USB 3.2.

The VIP for USB 3.2 provides support for USB 3.2 Hosts or Devices. It supports both super-speed-plus and super-speed modes and provides backward compatibility with USB 3.0 & 3.1, as per the specifications. The USB VIP 3.2 VIP license also grants users access to the Cadence USB 2.0 VIP. Currently, the VIP for USB 3.2 provides a serial signaling interface to test and monitor all possible configurations of USB 3.2 devices.

The VIP for USB 3.2 is compatible with all main verification languages (such as Verilog, SystemVerilog, and e) and industry-standard methodologies (such as UVM, OVM, and VMM), and runs on all leading simulators.

Specification Support

The specification is available at http://www.usb.org/developers/docs.

Key Features

List the key features from the spec that are implemented in the VIP. List the important ones in the table below.

Feature Name
Description
New Feature

Backward Compatibility

Supports backward compatibility with USB 2.0

Yes

Configurations

Supports Gen2x2, Gen1x2, Gen2x1, and Gen1x1

Yes

Physical Layer

  • Supports separate source clock per lane
  • Support for Gen1x2 8b10b encoding/decoding per lane
  • Support for Gen2x2 128b132b block encoding/decoding per lane
  • Support for LFSR per lane and enable/disable scrambling
  • Support for OS transmitted/received simultaneously on each negotiated lane
  • Support for Data Striping
  • Supports Gen2x2 Block Header Error with or without association
  • Supports Lane-Lane De-skew on Rx
Yes
Link Layer
  • Support for LFPS, LBPM, and SCD only on configuration lane
  • LTSSM support for Receiver detection only on configuration lane
  • Support for Ux Exit on configuration lane
  • LTSSM updates for eSS.Inactive, Rx.Detect, and Polling
  • LTSSM updates for U0, U1, U2, and U3
  • LTSSM updates for Recovery and Hot Reset
  • Increases the number of credits available from 4 to 7 for Gen2x2
Yes
Framework and Protocol Layer Updates value of Endpoint Companion and Isochronous Endpoint Companion descriptor type Yes
Re-Timer
  • Supports re-timer presence announcement in Host and Device VIP
  • Supports re-timer SKP number calculation in Host and Device VIP
Yes

 

Key Verification Capabilities

  • Compliance: Contains hundreds of protocol checks to verify that the DUT adheres to the protocol rules defined in the USB 3.2 Specification
  • Predefined error injections such as Crc5, Crc16, and Crc32 for header packets, link commands, data packets, discarding a packet, and so on
  • Callback capabilities are powerful; use callbacks to:
    • Change or corrupt the packet fields, or delay a packet to create time-out scenarios, and so on
    • Collect coverage
    • Scoreboard
  • Configuration is dynamic using SOMA or UVM Configuration
    • Change timing parameters to reduce simulation time
    • Control the functionality, such as changing the end-point configuration, polarity inversion, number of ordered sets to transmit/receive, and so on
  • Enumeration: Capability to bypass enumeration process, to do manual enumeration, or to enable auto enumeration process from the host VIP
  • Interface choice:
    • Serial
  • Register interface: 
    • To change the severity (Error, Warning, Info) of protocol assertions
    • To initiate low-power enter/exit sequences from the VIP
    • To control the functionality, such as end-point buffers, to exercise device flow control, streaming
    • To store VIP model information, such as device states, device address, end-point information, LTSSM states, and so on, which is easily accessible by the testbench
  • Traffic:
    • Generates all USB transactions as a host, like initiating bulk (including streaming), control, isochronous, and interrupt transfers
    • Responds to USB transactions as a device
    • LMP header packets
    • Full control on the device VIP to do flow control like sending NRDY or ERDY

Other Supported Features

Simulator Support IES, VCS, MTI

Testbench Language Interfaces

Verilog, SystemVerilog, e

UVM Agent

Yes

Trace Debug

Yes

Functional Coverage -  e

No

Functional Coverage - SystemVerilog

Yes

Dynamic Activation Yes

Compliance Management System

No

TripleCheck

 

RapidCheck

 

 

Supported Design-Under-Test Configurations

Host Device Hub/Switch
Full Stack Controller Only PHY Only

Training