Home: IP Portfolio > Verification IP > Simulation VIP > VIP for USB 3.1

VIP for USB 3.1

The Cadence® Verification IP (VIP) for USB 3.1 is a complete VIP solution for the Universal Serial Bus Revision 3.1 Specification and erratas. It provides a mature, highly capable compliance verification solution that supports simulation, formal analysis, and hardware acceleration platforms, making it applicable to intellectual property (IP), system-on-chip (SoC), and system-level verification. It provides full timing and bus functional modeling of USB 3.1.

The VIP for USB 3.1 provides support for USB 3.1 Hosts or Devices, or Hub. It operates in super-speed-plus mode and provides backward compatibility with super-speed and USB 2.0, as per the specifications. Currently, the Cadence VIP for USB 3.1 provides a serial signaling interface along with PIPE (MAC or MACRO) interfaces to test and monitor all possible configurations of USB 3.1 devices.

The Cadence VIP for USB 3.1 is compatible with all main verification languages (such as Verilog, SystemVerilog, e, VHDL, and Vera) and industry-standard methodologies (such as UVM, OVM, and VMM), and runs on all leading simulators.

Specification Support

The base specifications for the USB 3.1 protocol are available at http://www.usb.org/developers/docs.

Key Features

Key features from the spec that are implemented in the VIP are listed in the table below.



Backward Compatibility

Supports backward compatibility with superspeed and USB 2.0, in high- and full-speed modes

Bulk Stream Supports USB 3.1 bulk streaming protocol

Provides a complete USB protocol hierarchy enumeration process for host and device models

Link Training Supports USB 3.1 link training with all LTSSM state transitions and cover all arcs
LMP Supports link management packet flow
PTM Supports PTM messages
Low-Power Management Supports all low-power entry/exit sequences to U1, U2, and U3 states
Protocol Checks Does protocol checks at each layer, such as physical, link, protocol, and framework
Smart Isochronous Supports USB 3.1 smart isochronous transfers
Loopback Supports USB 3.1 loopback
Compliance Mode Supports USB 3.1 compliance mode
Hub Supports hub training, basic topology enumeration, packet routing, forwarding and reordering
Re-Timer Supports Re-timer BLR Compliance and Loopback from Host and Device models

Key Verification Capabilities

  • Compliance: Contains hundreds of protocol checks to verify that the DUT adheres to the protocol rules defined in the USB 3.1 Specification

  • Predefined error injections such as Crc5, Crc16, Crc32 for header packets, link commands, data packets, discarding a packet, etc.

  • Callback capabilities are powerful:

    • To change or corrupt the packet fields or delay a packet to create time-out scenarios, etc.

    • To collect coverage

    • To scoreboard

  • Configuration is dynamic using SOMA or UVM Confg

    • To change timing parameters to reduce simulation time

    • To control the functionality, such as changing the end-point configuration, polarity inversion, number of ordered sets to transmit/receive, etc.

  • Enumeration: Capability to bypass enumeration process, to do manual enumeration, or to enable auto enumeration process from the host VIP

  • Error injections: Predefined for cyclic redundancy check (CRC) for link commands, headers, and data packet payloads, discarding a packet, etc.

  • Interface choice: 

    • Serial

    • PIPE:  MAC, or MACRO with 8, 16, 32, or 64-bit PIPE width

  • Register interface: 

    • To change the severity (Error, Warning, Info) of protocol assertions

    • To initiate low-power enter/exit sequences from the VIP

    • To control the functionality, such as end-point buffers, to exercise device flow control, streaming

    • To store VIP model information, such as device states, device address, end-point information, LTSSM states, etc., which is easily accessible by the testbench

  • Traffic: 

    • Generates all USB transactions as a host, like initiating bulk (including streaming), control, isochronous (including smart isoch), and interrupt transfers

    • Responds to USB transactions as a device

    • LMP header packets

    • Full control on the device VIP to do flow control like sending NRDY or ERDY

 Other Supported Features

Assertion Coverage


Dynamic Activation Yes

Methodology Support

Complies with the Universal Verification Methodology (UVM), OVM, VMM

Platform Support

Operates in both simulated and accelerated platforms for ultimate flexibility

Simulator Support


Testbench Language Interfaces

Verilog, SystemVerilog, VHDL, Vera/NTB, e

UVM Agent Yes
RapidCheck Yes

Supported Design-Under-Test Configurations

Host Device Hub/Switch
Full Stack Controller Only PHY Only