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VIP for USB 3.0 and OTG

The Cadence® Verification IP (VIP) for USB 3.0 and OTG is a complete solution for the "Universal Serial Bus" Specification, Revision 2.0 and 3.0 and erratas. It provides a mature, highly capable compliance verification solution that supports simulation, formal analysis, and hardware acceleration platforms, making it applicable to intellectual property (IP), system-on-chip (SoC), and system-level verification. It provides full timing and bus functional modeling of USB 2.0 and USB 3.0.

The VIP for USB 3.0 and OTG provides support for any USB 2.0 or USB 3.0 device: Host, Hub or Device, or PHY. It operates in super-speed mode and provides backward compatibility with USB 2.0 as per the specifications. It provides multiple signaling interfaces: Serial, PIPE (MAC, MACRO, or PHY) to test and monitor all possible configurations of USB 3.0 devices.

The VIP for USB 3.0 and OTG is compatible with all main verification languages (such as Verilog, SystemVerilog, e, VHDL, and Vera) and industry-standard methodologies (such as UVM, OVM, and VMM), and runs on all leading simulators.

Specification Support

Key Features

FEATURE NAME

DESCRIPTION

Backward Compatibility Supports backward compatibility with USB 2.0, in high- and full-speed modes
All Transaction Types Supports all types of transfers: bulk, control, interrupt, and isochronous and split transactions
Bulk Stream Supports USB 3.0 bulk streaming protocol
Compliance State Supports all compliance patterns as part of Compliance LTSSM state
Enumeration Provides a complete USB protocol hierarchy enumeration process for host and device models
Link Training Supports USB 3.0 link training with all LTSSM state transitions and cover all arcs
LMP Supports link management packet flow
Loopback and BERT Supports PHY loop-back state with bit error rate test
Low-Power Management Supports all low power entry/exit sequences to U1, U2, and U3 states
OTG Support Supports OTG 1.3, 2.0, and 3.0 support and Role Swapping Protocol (RSP)
OTG Protocols Supports SRP (Session Request Protocol), ADP (Attach Detection Protocol), HNP (Host Negotiation Protocol), and RSP (Role Swapping Protocol)
Protocol Checks Does protocol checks at each layer, such as physical, link, protocol, and framework
Smart Isochronous Supports the USB 3.0 smart isochronous transfers
SSC Supports spread spectrum clocking
Hub Supports hub training, basic topology enumeration, packet routing and forwarding
Re-Timer Supports Re-Timer TS1A, TS1B OS, BLR compliance, and loopback from Host and Device models
Reset Signaling Supports spread spectrum clocking
Suspend/Resume Supports suspend, resume, remote wake-up, and low-power management (LPM)
UTMI+ Levels Supports all UTMI+ levels (1, 2, 3)

The following features from the spec are not yet supported:

  • Passive Hub modelHub with HSIC interface
  • Hub with HSIC interface
  • OTG 3.0 Interoperability with OTG 2.0

Key Verification Capabilities

  • Compliance: Contains hundreds of protocol checks to verify that the DUT adheres to the protocol rules defined in the USB 2.0 and 3.0 Specification

  • Predefined error injections such as Crc5, Crc16, Crc32 for header packets, link commands, data packets, discarding a packet, etc.

  • Callback capabilities are powerful:

    • To change or corrupt the packet fields or delay a packet to create time out scenarios, etc.
    • To collect coverage
    • To scoreboard
  • Configuration is dynamic using SOMA:

    • To change timing parameters to reduce simulation time
    • To control the functionality, such as changing the end-point configuration, polarity inversion, number of ordered sets to transmit/receive, etc.
  • Enumeration: Capability to bypass enumeration process, to do manual enumeration, or to enable auto enumeration process from the host VIP

  • Error injections: Predefined for cyclic redundancy check (CRC) for link commands, headers, and data packet payloads, 8b10b errors, discarding a packet, etc.

  • Interface choice:

    • Serial
    • PIPE:  MAC, PHY, or MACRO (include-PHY) with 8, 16, or 32-bit PIPE width
    • DPDM
    • HSIC
    • UTMI/UTMI+: MAC or MACRO (include-PHY) with 8 or 16-bit data width
    • ULPI: MAC or MACRO
  • Register interface: 

    • To change the severity (Error, Warning, Info) of protocol assertions
    • To initiate low-power enter/exit sequences from the VIP
    • To control the functionality, such as end-point buffers, to exercise device flow control, streaming
    • To store VIP model information, such as device states, device address, end-point information, LTSSM states, etc., which is easily accessible by the testbench
  • Traffic: 

    • Generates all USB transactions as a host like initiating bulk (including streaming), control, isochronous (including smart isoch), interrupt transfers

    • Responds to USB transactions as a device

    • LMP header packets

    • Full control on the device VIP to do flow control like sending NRDY, ERDY

Other Supported Features

Assertion Coverage

Yes

Functional Coverage

SystemVerilog

Platform Support

Operates in both simulated and accelerated platforms for ultimate flexibility

RapidCheck Yes
TripleCheckTM Yes
UVM Agent Yes

Training, Documentation, and Usage Information

See the "Verification IP" page of Cadence Online Support for training, documentation, and usage information.

 

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