Home: IP Portfolio > Verification IP > Simulation VIP > VIP for USB 2.0 + OTG

VIP for USB 2.0 + OTG

The Cadence® Verification IP (VIP) for USB 2.0 + OTG  is a complete VIP solution for the "Universal Serial Bus" Specification, Revision 2.0, and "On The Go" supplement for USB revision 2.0 specifications and erratas. It provides a mature, highly capable compliance-verification solution that supports simulation, formal analysis, and hardware acceleration platforms, making it applicable to intellectual property (IP), system-on-chip (SoC), and system-level verification. It provides full timing and bus functional modeling of USB 2.0 and USB 2.0 OTG.

This VIP for USB 2.0 + OTG provides support for any USB 2.0 device: Host, Hub or Device. It supports all USB 2.0 operational speeds: Low, Full, or High. It provides multiple signaling interfaces: DpDm, HSIC, UTMI/UTMI+, and ULPI  to test and monitor all possible configurations of USB devices. It provides support to both OTG 1.3 and OTG 2.0 revisions.

The VIP for USB 2.0 + OTG is compatible with all main verification languages (such as Verilog, SystemVerilog, e, VHDL, C, SystemC®, and Vera) and industry-standard methodologies (such as UVM, OVM, VMM), and runs on all leading simulators.


The specifications for the USB 2.0 and OTG 2.0 protocols are available at http://www.usb.org/developers/docs.

See also:

Key Features

The VIP for USB 2.0 + OTG can be used to verify all device types: Host, Hub, or Device. It provides active Host, Device, and Hub VIP models, as well as passive Host and Device models. The signaling interface can be selected to be either DpDm, HSIC, UTMI/UTMI+, or ULPI. Note that HSIC is currently not supported for Hubs.



All transaction types

Supports all types of transfers: bulk, control, interrupt, and isochronous and split transactions

Backward compatible

Backwards compatible with USB 1.1 specifications


Provides a complete USB protocol hierarchy enumeration process for host, device, and hub models

Operational speed

Operates at high, full, or low speed

OTG support

Supports OTG 1.3 and OTG 2.0 revisions with both A-device and B-device configurations

OTG protocols

Supports SRP (Session Request Protocol), ADP (Attach Detection Protocol), and HNP (Host Negotiation Protocol)

Reset signaling

Supports reset and high-speed chirp handshake


Supports suspend, resume, remote wake-up, and low-power management (LPM)

Transaction and packet checks

Checks for all transaction and packet rules including inter-packet gap and propagation delays

UTMI+ levels

Supports all UTMI+ levels (1, 2, 3)

Key Verification Capabilities

  • Compliance: Contains hundreds of protocol checks to verify that the DUT adhere to the protocol rules defined in the USB 2.0 Specification
  • Callback capability is powerful:
    • To change or corrupt the packet fields or delay the packet
    • To collect coverage
    • To score-board
  • Dynamic SOMA configuration:
    • To change timing parameters to reduce simulation times
    • To control the functionality such as changing the end-point configuration, disable retry or PING protocol
  • Enumeration: Capability to bypass enumeration process, to do manual enumeration, or to enable auto enumeration process from the host VIP
  • Error injections are predefined for Crc, Pid (PidInv) or to discard a packet
  • Interface choice:
    • DPDM
    • HSIC
    • UTMI/UTMI+: MAC or MACRO (include-PHY) with 8 or 16-bit data width
    • ULPI: MAC or MACRO
  • Platforms: Operates in both simulated and accelerated platforms for ultimate flexibility
  • Register interface:
    • To change the severity (Error, Warning, Info) of the protocol assertions
    • To initiate various commands such as reset, suspend/resume/remote wake-up, disconnect/connect, and OTG commands such as SRP, HNP, PowerDown, etc.
    • To control the functionality such as end-point buffers, chirp sequence, clock frequency
    • To store information of the VIP model such as device states, device address, end-point information, etc., which is easily accessible by the testbench
  • Traffic:
    • Generates all USB transactions as a host like initiating bulk, control, isochronous, interrupt transfers
    • Responds to USB transactions as a device
    • LPM packets
    • Full control on the device VIP to do flow control like sending NAK, NYET
    • Split transactions

 Other Supported Features

Testbench Language Interfaces Verilog, SystemVerilog, VHDL, Vera/NTB, e, C/C++ SystemC
Simulator Support IES, VCS, MTI
Methodology Support Universal Verification Methodology (UVM), OVM, and VMM
UVM Agent Yes
Trace Debug Yes
Assertion Coverage Yes
Functional Coverage - SV Part of PureSuite
Compliance Management System _

Supported Design-Under-Test Configurations

Host Device Hub/Switch
Full Stack Controller Only PHY Only

Test Suite Options

Basic CMS PureSuite TripleCheck


Test Suite Comparison

Constrained-random example tests
Directed compliance tests
Constrained-random compliance tests
Tests targeting all protocol layers
3rd party simulator test execution
SystemVerilog functional coverage model
efunctional coverage model
Verification plan mapped to protocol specification
Verification plan integration with Cadence vManager metric-driven analysis system
Verification plan integration with 3rd party simulator environments

User Feedback

"The Cadence SuperSpeed USB VIP has helped PLDA to be one of the first IP vendors to reach the market, while ensuring it is among the highest quality products available. Using Cadence VIP has enabled PLDA to achieve significantly greater functional coverage results."
- Stephane Hauradou, Chief Technology Officer, PLDA