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VIP for Embedded USB2 (eUSB2)

The Cadence® Verification IP (VIP) for eUSB is a complete VIP solution for the Embedded USB2 (eUSB2) Physical Layer Supplement to the USB Revision 2.0 Specification, Revision 1.1. It provides a mature, highly capable compliance-verification solution that supports simulation, making it applicable to intellectual property (IP), system-on-chip (SoC), and system-level verification. It provides full-timing and bus functional modeling of eUSB Native Mode.

This VIP for eUSB provides support for any eUSB device in native mode: Host(eDSPn) or Device(eUSPn). It supports all eUSB operational speeds: Low, Full, or High. It provides multiple signaling eUSB interfaces: single-ended signaling for low-/full-speed mode and low-voltage differential signaling for high-speed mode to test and monitor all possible configurations of USB devices.

The VIP for eUSB is compatible with all main verification languages (such as SystemVerilog ) and industry-standard methodologies (such as UVM, OVM, VMM), and runs on all leading simulators.

Specification Support

The specifications for the eUSB protocols are available at http://www.usb.org/developers/docs.

Protocol Features

The VIP for eUSB can be used to verify all device types: Host(eDSPn) or Device(eUSPn). It provides active Host and Device VIP models.

 
Description

All Transaction Types

Supports all types of transfers: bulk, control, interrupt, and isochronous transactions

Backward Compatible

Supports backward compatibility with USB 1.1 specifications

Enumeration

Provides a complete USB protocol hierarchy enumeration process for host and device models

 

Operational Speed

Operates at high, full, or low speed

 

Reset Signaling

Supports low/full-speed reset and high-speed chirp handshake

Suspend/Resume

Supports suspend, resume, remote wake-up, and low-power management (LPM)

Transaction and Packet Checks

Checks for all transaction and packet rules including inter-packet gap and propagation delays

Key Verification Capabilities

  • Compliance: Contains hundreds of protocol and physical checks to verify that DUT adheres to the protocol rules defined in the USB 2.0 Specification and eUSB Specification respectively
  • Callback capability is powerful:

    • To Change or corrupt the packet fields or delay the packet

    • To collect coverage

    • Collect coverage

    • To scoreboard

  • Dynamic SOMA configuration:

    • To change timing parameters to reduce simulation times
  • Enumeration: Capability to bypass the enumeration process, to do manual enumeration, or to enable auto enumeration process from the host VIP

  • Digital translator available for sending eUSB-compliant traffic

  • Error injections are predefined as follows:

    • Device drives Port Reset during POR

    • Host drive ED+ as 1 instead of driving SE1 in Port Reset

    • Device corrupts the ACK in Port Configuration

    • Device drives invalid Connect Signal depending on the speed of operation

    • Device drives invalid ping

    • Host does not send an EOP

    • Host drives J signal instead of K during the resume operation

    • Host does not drive Resume signal after Remote wakeup from device

    • Host sends corrupted EOP to the device

  • Register interface:

    • To change the severity (Error, Warning, Info) of the protocol assertions

    • To initiate various commands such as reset, suspend/resume/remote wake-up, disconnect/connect, and so on

    • To control the functionality such as end-point buffers, chirp sequence, and clock frequency

    • To store information of the VIP model such as, device states, device address, end-point information, and other information that is easily accessible by the testbench

    • To insert error injections at the eUSB Phy

    • To go to Port Reset from any state, issue silent and soft disconnect by device (eUSPn)

  • Traffic:

    • Generates all USB transactions as a host and device like initiating bulk, control, isochronous, interrupt transfers with eUSB signaling

    • LPM packets

    • Full control on the device VIP to do flow control like sending NAK and NYET

Other Supported Features

Simulator support

Xcelium™, VCS, and MTI

Testbench Language Interface

SystemVerilog

Methodology

Universal Verification Methodology (UVM)

Trace debug

Yes

Training, Documentation and Usage Information

See the Verification IP Support Home on Cadence Online Support for training, documentation, and usage information.

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