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VIP for NVM Express

Specification Support

The Cadence® Verification IP (VIP) for NVMe 1.3 and NVMe 1.4 are part of Cadence's storage interface VIP portfolio. It provides a mature and highly capable compliance verification solution for the NVM Express (NVMe) protocol. It is applicable for IP, SoC, and system-level verification. The VIP is compatible with industry-standard Universal Verification Methodology (UVM), and runs on the Cadence Incisive Enterprise Simulator as well as well as on third-party simulators.

The Cadence VIP for NVMe 1.4 supports the NVMe Specification Revision 1.4, which can be downloaded at http://www.nvmexpress.org/specifications. It also includes updates for NVMe 1.3a, NVme 1.3b, NVMe 1.3c, and NVMe 1.3d.

Protocol Features

FEATURE NAME

DESCRIPTION

Admin Command Set

Supports all of the mandatory Admin Command set, which defines the commands that can be submitted to the Admin Submission Queue.

NVM Command Set

Supports all of the mandatory NVM command set. The NVM command set is a specification-defined I/O command set used with an I/O queue pair.

I/O Queue

Configurable I/O submission/completion queues:

  • Up to 64K queues

  • Each queue supports up to 64K outstanding commands

Admin Queue

Configurable Admin submission/completion queues

Controller-Level Reset

CC.EN transitions from '1' to '0'

Subsystem-Level Reset

Support for NVM Subsystem Reset

Command Arbitration

Configurable command arbitration schemes:

  • Round robin

  • Weighted round robin

  • Vendor specific

Interrupt Support

  • Pin based

  • MSI (single and multiple message)

  • MSI-X

Multi-Path I/O

Support for two or more completely independent PCIe paths between single host and namespace

Namespace Sharing

Support for two or more hosts to access common shared namespace

Namespace Management

Support of Namespace management command used to create/delete namespace

NVMe 1.3

PRP Entry and List

Supports physical region page (PRP) entry that points to physical memory page

Scatter Gatter List

Supports scatter gather list (SGL)

Sanitize (optional)

Supports sanitize operation in which all user data in the NVM subsystem is altered such that recovery from any cache or the non-volatile media is not possible

Directives (optional)

Supports the directives mechanism that allows the exchange of information between host and NVM subsystem or controller

Boot Partitions

Boot partition support by controller

Telemetry

Device reports telemetry opaque data that is initiated by either the host or controller

Virtualization

Supports virtualization management command

Device Self-Test

Supports device self-test command to start or abort self-test operation

Host-Controlled Thermal Management

Supports thermal management actions

Timestamp

Enables host to set timestamp value in the controller

Emulated Controller Performance Enhancement

Supports doorbell buffer config command

NVMe 1.4

Verify Command

Support of the Verify command. This command verifies teh integrity of the store information by reading data and meta-data

Persistent Memory Region

Support persistent memory region (PMR). This is an optional region of general purpose PCIe read/write memory that can be used for variety of purposes

Key Verification Capabilities

  • Standalone NVMe mode

  • NVMe over PCIe

  • NVMe over AXI

Topologies Supported

VIP as NVMe Host (over PCIe)

 

VIP as NVMe Subsystem (over PCIe)

 

Other Supported Features

Simulator Support

IES, third-party

Testbench Language Interface

SystemVerilog

Methodology

SV-UVM

UVM

Yes

Trace Debug

Yes

Functional Coverage - e

No

Functional Coverage - SystemVerilog

In Progress

Dynamic Activation

N/A

Compliance

N/A

TripleCheck

In Progress

RapidCheck

In Progress

Interconnect Validator

N/A

Accelerated Validator

No

Test Suite Options

Basic CMS PureSuite TripleCheck

 

Test Suite Comparison

 BasicCMSPureSuiteTripleCheck
Constrained-random example tests
Directed compliance tests
Constrained-random compliance tests
Tests targeting all protocol layers
3rd party simulator test execution
SystemVerilog functional coverage model
efunctional coverage model
Verification plan mapped to protocol specification
Verification plan integration with Cadence vManager metric-driven analysis system
Verification plan integration with 3rd party simulator environments