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PCIe SR-IOV Simulation Verification IP (VIP)

Specification Support

The Cadence SR-IOV VIP provides a means to form and operate a SR hierarchy and the ability to generate and check related traffic per virtual function. This product complements the PCI-Express (PCIe) VIP.

The SR-IOV VIP is a higher layer above the PCI-Express (PCIe) VIP. It enables the definitions of virtual functions (VF) and physical functions (PF), and an active SR-PCIM performs checks for related traffic.

Product Highlights

  • Part of a complete PCI Express solution including:
    • PCI Express Gen3
    • PCI Express Gen2
    • NVM Express
    • Mobile PCI Express
    • SR-IOV
    • MR-IOV
  • Supports the latest specification ECNs

Key Features

Feature Name
Description

Generate traffic to target all functionality defined by the spec

 Supported

EROM Supports access to PF EROM
Function level reset Per VF FLR
VF migration Supported
ARI Alternative routine ID
VF sharing header log files VF can use the same header log files

Supported Design-Under-Test Configurations

Master Slave Hub/Switch
Full Stack Controller Only PHY Only

Test Suite Options

Basic CMS PureSuite TripleCheck

 

Test Suite Comparison

 BasicCMSPureSuiteTripleCheck
Constrained-random example tests
Directed compliance tests
Constrained-random compliance tests
Tests targeting all protocol layers
3rd party simulator test execution
SystemVerilog functional coverage model
efunctional coverage model
Verification plan mapped to protocol specification
Verification plan integration with Cadence vManager metric-driven analysis system
Verification plan integration with 3rd party simulator environments