Home: IP Portfolio > Verification IP > Simulation VIP > PCIe MR-IOV Simulation VIP

PCIe MR-IOV Simulation Verification IP (VIP)

Specification Support

MR-IOV supports the Multi-Root I/O Virtualization and Sharing Specification Revision 1.0. The spec can be downloaded only by members of the PCI-SIG website: http://www.pcisig.com/home

Product Highlights

  • Industry's first MR-IOV VIP
  • Part of a complete PCI Express solution including:
    • PCI Express Gen3
    • PCI Express Gen2
    • NVM Express
    • Mobile PCI Express
    • SR-IOV
    • MR-IOV
  • Supports the latest specification ECNs

Key Features

Feature Name
Description

Virtual link

VL=0

TLP prefix tagging generation Addition of the MR prefix to TLPs
Per-VH reset  Supported
Message processing INTx\PM
Base error detection and logging  Supported
MRA switch hot plug  Supported
Congestion management  Supported

Supported Design-Under-Test Configurations

Master Slave Hub/Switch
Full Stack Controller Only PHY Only

Test Suite Options

Basic CMS PureSuite TripleCheck

 

Test Suite Comparison

 BasicCMSPureSuiteTripleCheck
Constrained-random example tests
Directed compliance tests
Constrained-random compliance tests
Tests targeting all protocol layers
3rd party simulator test execution
SystemVerilog functional coverage model
efunctional coverage model
Verification plan mapped to protocol specification
Verification plan integration with Cadence vManager metric-driven analysis system
Verification plan integration with 3rd party simulator environments