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Verification IP for PCI Express 5.0

The Cadence® Verification IP (VIP) for PCI Express® (PCIe®) 5.0 supports a wide range of verification platforms, all major simulators, and the industry-standard Universal Verification Methodology (UVM). The VIP core is written in native C for excellent performance, with seamless integration with all verification languages - SystemVerilog, e, Verilog, VHDL, and SystemC®.

In addition to all that is offered in the VIP for PCI Express 1.1 and 2.0, the VIP for PCI Express 3.0, and the VIP for PCI Express 4.0, the VIP for PCIe 5.0 adds Gen 5-related checks and controls.

Specification Support

The VIP is compliant with PCI Express specification 5.0 revision 1.0.

The specification can be downloaded only by members of the PCI-SIG website: http://www.pcisig.com/home.

Product Highlights

The capabilities below are additive to PCI Express 1.1 and 2.0PCI Express 3.0, and PCI Express 4.0

  • Operates at 32GT/s
  • EIEOS changes for Gen 5
  • TS1/TS2 OS changes for Gen 5
  • Equalization bypass capability
  • Precoding support
  • Supports both PIPE 5.x and serial interfaces

Key Features

Important features offered in the Cadence VIP for PCIe 5.0 are listed in the table below.

Feature Name

Device Type

Root Complex, End Point, Legacy End Point, Switch, PHY DUT, Bridge

Interface Serial, Parallel, PIPE 5.0
Link Rate

Supports all PCIe speeds: 2.5GT/s, 5.0GT/s, 8.0GT/s, 16GT/s, 32.0GT/s

Gen 5 support per revision 0.7 specification

  • Gen 4 (16GT/s) to Gen 5 (32 GT/s) speed change path
  • EIEOS symbol change
  • TS1/TS2 OS changes to support Gen 5
  • Equalization updates (including equalization bypass capability for Gen 5)
  • Polling Compliance updates
  • Precoding support
Link Width

Configurable link width support x1, x2, x4, x8, x16, x32

Full support for up and down configuration

Virtual Channel Automatic or user-defined flow control initialization per virtual channel
Side-Band Signal Support WAKE#, CLKREQ#, PERST#
Protocol Timers
  • Full configurability
  • ACK, NAK, Replay timer simplification for Gen 4.0
Fault Isolation

Advanced error reporting (AER) to assist in fault isolation and root cause analysis

Equalization Perform and control all equalization flow for all PCIe generations (Gen 1.0 to Gen 4.0)
Flow Control Credit (FCC)

Full control of flow control credits

  • Gen 4.0 support for flow control scaling
  • Initial allocation of FCCs
  • Dynamic FCC updates
Retimer Support Root Complex and End Point support for recognizing retimer in the topology, Retimer Model (active and passive) not available
Tag Scaling 10-bit extended tag support to increase number of outstanding non-posted requests
Rx Margining Lane margining at receiver for 16GT/s
Clock Compensation Gen 4.0 updated SKP OS support
Elastic Buffer Mode Ability to control the elasticity buffer operating mode: Nominal Half Full/Nominal Empty
Electrical Idle Infer electrical idle condition for all PCIe generations (Gen 1.0 to Gen 4.0)

Complete link training status state machine (LTSSM) modeling

  • Configuration states
  • Power saving states
  • Recovery states

Ability to insert skew between lanes

Clock Recovery

Clock recovery mechanisms supported:

  • Incoming bit stream
  • Reference clock
Clock Jitter Ability to add jitter to clock
Address Space

Support for all types of address spaces:

  • Memory
  • I/O
  • Configuration
Function Level Reset Full compliance
ECN Support
  • PASID Translation 
  • Multicast
  • Latency Tolerance Reporting (LTR)
  • TLP Prefix
  • TLP Processing Hints
  • Optimized Buffer Flush/Fill
  • ASPM Optionality
  • Protocol Multiplexing (PMUX)
  • Separate Refclk Independent SSC Architecture (SRIS)
  • L1 PM substate with CLKREQ
  • Expanded Resizable BAR
PIPE Support

PIPE 5.0 support

Other Supported Features


Testbench Language Interfaces

SystemVerilog, eVerilog, VHDL, and SystemC 

UVM Agent


Trace Debug


Functional Coverage -  e


Functional Coverage - SV


Compliance Management System




Interconnect Validator


Supported Design-Under-Test Configurations

Root Complex End Point Switch/Bridge
Full stack Controller-only PHY-only

Test Suite Options

Basic CMS PureSuite TripleCheck

Test Suite Comparison

Constrained-random example tests
Directed compliance tests
Constrained-random compliance tests
Tests targeting all protocol layers
3rd party simulator test execution
SystemVerilog functional coverage model
efunctional coverage model
Verification plan mapped to protocol specification
Verification plan integration with Cadence vManager metric-driven analysis system
Verification plan integration with 3rd party simulator environments