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VIP for PCI Express

The Cadence® Verification IP (VIP) for PCI Express® (PCIe®) provides a complete bus functional model (BFM) with thousands of integrated automatic protocol checks for all three protocol layers (TL, DLL, PL) in addition to specific PIPE and PIE. Designed for easy integration in test benches at IP, SoC, and system levels, the VIP helps engineers reduce time to first test, accelerate verification closure, and ensure end-product quality.

The VIP for PCIe can be used stand-alone or as a platform for running TripleCheck tests, and\or for enabling MR-IOV, SR-IOV, CCIX, CXL, or NVMe on top of the base VIP. The VIP for PCIe supports a wide range of verification platforms, all major simulators, and the industry-standard Universal Verification Methodology (UVM). The VIP core is written in native C language for excellent performance, with seamless integration with all verification languages—SystemVerilog, e, Verilog, VHDL, and SystemC®.


The VIP is compliant with PCI Express specification versions 5.0, 4.0, 3.0, 2.1, 2.0 and 1.1.

The specification can be downloaded only by members of the PCI-SIG website: http://www.pcisig.com/home.

Protocol Features

Important features offered in the Cadence VIP for PCIe 5.0 are listed in the table below.

Feature Name
New Feature

Device Type

Root Complex, End Point, Legacy End Point, Switch, PHY DUT, Bridge


Interface Serial, Parallel (8-bit, 10-bit, 128-bit, and 130-bit), PIE8, PIPE 3.0, PIPE 4.0, PIPE 4.3, PIPE 5.2 (Low Pin-count I/F), SerDes mode Yes
Link Rate

Supports all PCIe speeds: 2.5GT/s, 5.0GT/s, 8.0GT/s, 16GT/s, 32.0GT/s

Gen 5 support per revision 0.7 specification

  • Gen 4 (16GT/s) to Gen 5 (32 GT/s) speed change path
  • EIEOS symbol change
  • TS1/TS2 OS changes to support Gen 5
  • Equalization updates (including equalization bypass capability for Gen 5)
  • Polling Compliance updates
  • Precoding support
Link Width

Configurable link width support x1, x2, x4, x8, x16, x32

Full support for up and down configuration

Virtual Channel Automatic or user-defined flow control initialization per virtual channel
Side-Band Signal Support WAKE#, CLKREQ#, PERST#
Protocol Timers
  • Full configurability
  • ACK, NAK, Replay timer simplification for Gen 4.0
Fault Isolation

Advanced error reporting (AER) to assist in fault isolation and root cause analysis

Equalization Perform and control all equalization flow for all PCIe generations (Gen 1.0 to Gen 5.0) Yes
Flow Control Credit (FCC)

Full control of flow control credits

  • Flow control scaling introduced in Gen 4
  • Initial allocation of FCCs
  • Dynamic FCC updates
Retimer Support Root Complex and End Point support for recognizing retimer in the topology, Retimer Model (active and passive) not available
Tag Scaling 10-bit extended tag support to increase number of outstanding non-posted requests
Rx Margining Lane margining at receiver for 16GT/s Yes
Clock Compensation Gen 4.0 updated SKP OS support
Elastic Buffer Mode Ability to control the elasticity buffer operating mode: Nominal Half Full/Nominal Empty
Electrical Idle Infer electrical idle condition for all PCIe generations (Gen 1.0 to Gen 5.0) Yes

Complete link training status state machine (LTSSM) modeling

  • Configuration states
  • Power saving states
  • Recovery states

Ability to insert skew between lanes

Clock Recovery

Clock recovery mechanisms supported:

  • Incoming bit stream
  • Reference clock
Clock Jitter Ability to add jitter to clock
Address Space

Support for all types of address spaces:

  • Memory
  • I/O
  • Configuration
Ack\Nak Predefined sequence number, link CRC (LCRC), and duplicate TL error injections
Function Level Reset (FLR) Full compliance
Interrupts Handles interrupt mechanisms (MSI, MSI-X, INTx)
Power management Full power management support (D-states, L-States, ASPM)
ECN Support
  • Process Address Space ID (PASID)
  • PASID Translation
  • Alternative Routing-ID Interpretation (ARI)
  • Atomic Operations
  • Resizable BAR Capability
  • Multicast
  • Dynamic Power Allocation
  • ID-Based Ordering
  • Latency Tolerance Reporting (LTR)
  • Extended Tag Enable Default
  • TLP Processing Hints
  • TLP Prefix
  • Optimized Buffer Flush/FIll (OBFF)
  • ASPM Option
  • End-End TLP Prefix Changes for RC
  • Protocol Multiplexing (PMUX)
  • Separate Refclk Independent SSC Architecture (SRIS)
  • Precision Time Measurement (PTM) Revision 1.0
  • L1 PM sub-state with CLKREQ
  • Designated Vendor-Specific Extended Capability (DVSEC)
  • Expanded Resizable BAR
  • VF Resizable BAR
Updated to include Gen 1 and 2 ECN
PIPE Support

PIPE 3.0, PIPE 4.0, PIPE 4.3, PIPE 5.2 support

  • SerDes mode
  • RxValid synchronous to RxCLK in SerDes mode
  • Loopback updates including equalization bypass (for lanes under test)

Key Verification Capabilities

  • Gen 1.1, 2.0, 3.0
    • Injecting and checking framing tokens errors
    • DC Balance checks and coverage
    • Equalization procedure support, error injection and checks.
    • 128b/130b encoding scheme checks
  • Gen 4.0
    • Operates at 16 GT/s
    • Multi-Lane Rx Error reporting per lane in the Lane Error Status register
    • Inferring of EI for 16 GT/s
    • Tag Scaling
    • Flow Control Scaling
    • Rx Margining
  • Gen 5.0
    • Operates at 32GT/s
    • EIEOS changes for Gen 5
    • TS1 and TS2 OS changes for Gen 5
    • Equalization bypass capability
    • Precoding support
    • Supports both PIPE 5.x and serial interfaces

Other Supported Features

UVM Agent Yes
Trace Debug Yes
Functional Coverage - SV Yes
TripleCheck Yes
Save & Restore (IES only) Yes
Performance report Yes
Accelerated VIP Yes

Training, Documentation, and Usage Information

See the Verification IP Support Home for more information.