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Verification IP for PCI Express 5.0

The Cadence® Verification IP (VIP) for PCI Express® (PCIe®) 5.0 supports a wide range of verification platforms, all major simulators, and the industry-standard Universal Verification Methodology (UVM). The VIP core is written in native C for excellent performance, with seamless integration with all verification languages - SystemVerilog, e, Verilog, VHDL, and SystemC®.

In addition to all the VIP for PCI Express 1.1 and 2.0, the VIP for PCI Express 3.0, and the VIP for PCI Express 4.0 have to offer, the VIP for PCIe 5.0 adds Gen 5-related checks and controls.

Specification Support

The VIP supports PCI Express specification 5.0 rev 0.3

The specification can be downloaded only by members of the PCI-SIG website: http://www.pcisig.com/home.

Key Features

Feature Name

Device type 

Root Complex, End Point, Legacy End Point, Switch, PHY DUT, Bridge


Serial, Parallel, PIPE 4.4

Link rate


Supports all PCI Express speeds: 2.5 GT/s, 5.0 GT/s, 8.0 GT/s, 16 GT/s

Gen 5 support per rev 0.3 specification
  • Gen 4 (16GT/s) to Gen 5 (32 GT/s) speed change path
  • EIEOS symbol change
  • TS1/TS2 OS changes to support Gen 5

Link width

Configurable link width support x1, x2, x4, x8, x16, x32

Full support for up and down configuration

Virtual channel

Automatic or user-defined flow control initialization per virtual channel

Side-band signal support


Protocol timers

• Full configurability

• ACK, NAK, Replay timer simplification for Gen 4.0

Fault Isolation 

Advanced error reporting (AER) to assist in fault isolation and root cause analysis


Perform and control equalization flow for all PCIe generations (Gen 1.0 to Gen 4.0)

Flow control credit (FCC)

Full control of flow control credits 

  • Gen 4.0 support for flow control scaling
  • Initial allocation of FCCs
  • Dynamic FCC updates

Retimer Support 

Root complex and End Point support for recognizing retimer in the topology, Retimer Model (active and passive) not available

Tag Scaling 

10-bit extended tag support to increase number of outstanding non-posted requests

Rx Margining 

Lane margining at receiver for 16GT/s

Clock compensation 

Gen 4.0 updated SKP OS support
Elastic Buffer Mode Ability to control the elasticity buffer operating mode: Nominal Half Full/Nominal Empty
Electrical Idle Infer electrical idle condition for all PCIe generations (Gen 1.0 to Gen 4.0)


Complete link training status state machine (LTSSM) modeling

  • Configuration states
  • Power saving states
  • Recovery states

Ability to insert skew between lanes

Clock Recovery

Clock recovery mechanisms supported

1. Incoming bit stream

2. Reference clock

 Clock Jitter

Ability to add jitter to clock

Address space

Support for all types of address spaces

  • Memory
  • I\O
  • Configuration

Function Level Reset

Full compliance

ECN support

  • PASID Translation 
  • Multicast
  • Latency Tolerance Reporting (LTR)
  • TLP Prefix
  • TLP Processing Hints
  • Optimized Buffer Flush/Fill
  • ASPM Optionality
  • Protocol Multiplexing (PMUX)
  • Separate Refclk Independent SSC Architecture (SRIS)
  • L1 PM substate with CLKREQ
  • Expanded Resizable BAR

Key Verification Capabilities

The capabilities below are additive to PCI Express 1.1 and 2.0 and PCI Express 3.0 and PCI Express 4.0

  • Operates at 32 GT/s
  • EIEOS changes for Gen 5
  • TS1/TS2 OS changes for Gen 5
  • Supports both PIPE and serial interfaces


Supported Design-Under-Test Configurations

Root Complex End Point Switch/Bridge
Full stack Controller-only PHY-only

Test Suite Options

Basic CMS PureSuite TripleCheck

Test Suite Comparison

Constrained-random example tests
Directed compliance tests
Constrained-random compliance tests
Tests targeting all protocol layers
3rd party simulator test execution
SystemVerilog functional coverage model
efunctional coverage model
Verification plan mapped to protocol specification
Verification plan integration with Cadence vManager metric-driven analysis system
Verification plan integration with 3rd party simulator environments