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PCI Express Gen3 Simulation Verification IP (VIP)

Specification Support

The VIP is fully compliant with the 3.0 revision of the PCI Express spec, and the ECNs listed below.

Product Highlights

  • Part of a complete PCI Express solution including:
    • PCI Express Gen3
    • PCI Express Gen2
    • NVM Express
    • Mobile PCI Express
    • SR-IOV
    • MR-IOV
  • Supports the latest specification ECNs
  • Optional TripleCheck product provides a complete pre-silicon compliance testing solution
  • Includes all features of Cadence VIP for PCI Express Gen2 Simulation VIP

  • Features optional Accelerated VIP

Key Features

Feature Name
Description

Equalization Procedure

Perform and control all equalization aspects

DC Balance Full support for the new TS symbols
Framing Tokens Error injection, checking, and coverage
Clock Compensation New Skip OS full support
PMUX Protocol multiplexing ECN
OBFF Optimized buffer flush\fill
ASPM Optionality ASPM optionality ECN
L1 PM Substates L1 substates ECN
DPC Downstream port containment ECN
LN Lightweight notification ECN
M-PCIE PCIe over M-PHY ECN
PASID Process address space ID ECN
PTM Precision time measurement ECN
SRIS

Separate Refclk Independent SSC Architecture

PIPE 4.3 PHY Interface for the PCI Express* (PIPE) Architecture Revision 4.3

Supported Design-Under-Test Configurations

Root Complex End Point Switch/Bridge
Full stack Controller-only PHY-only

Test Suite Options

Basic CMS PureSuite TripleCheck

 

Test Suite Comparison

 BasicCMSPureSuiteTripleCheck
Constrained-random example tests
Directed compliance tests
Constrained-random compliance tests
Tests targeting all protocol layers
3rd party simulator test execution
SystemVerilog functional coverage model
efunctional coverage model
Verification plan mapped to protocol specification
Verification plan integration with Cadence vManager metric-driven analysis system
Verification plan integration with 3rd party simulator environments

User Feedback

"Wipro has been consistently enabling semiconductor companies to reduce verification time and increase coverage parameters through its next-generation frameworks and market-proven end-to-end verification services. Our partnership with Cadence has played an instrumental role in fulfilling the IP verification needs of our customers. We chose PCIe Gen3 VIP along with TripleCheck by Cadence to achieve a comprehensive solution that gives us the fastest path to IP verification closure."
- A. Vasudevan, VP Semiconductor and Systems, Wipro

"We’ve determined that 90% of the risk is in the chip’s interfaces. If we design the interfaces incorrectly, it doesn’t matter if we get the rest of the chip right. This is especially true with PCI Express since it’s such a complex protocol. The bottom line for us is that the choice we made to go with proven IP that’s easy to get up and running is really just good, solid common sense. "
- Jim O’Connor, Vice President of Engineering, iVivity