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PCI Express Gen2 Simulation Verification IP (VIP)

Specification Support

This VIP is fully compliant with the 2.1 revision of the PCI Express specification.

The specification can be downloaded only by PCI-SIG members from the SIG website: http://www.pcisig.com/home.

Product Highlights

  • Part of a complete PCI Express solution including:
    • PCI Express Gen3
    • PCI Express Gen2
    • NVM Express
    • Mobile PCI Express
    • SR-IOV
    • MR-IOV
  • Supports the latest specification ECNs
  • Optional TripleCheck product provides a complete pre-silicon compliance testing solution
  • Features optional Accelerated VIP

Key Features

Feature Name
Description

Number of lanes

Supports x1, x2, x4, x8, x12, x16, and x32 lanes

LTSSM modeling and checking Complete link training status state machine (LTSSM) modeling, including all configuration, power-saving, and recovery states
Speed negotiation Full control of the link speed, up and down changes
Up-configuration Full support for up and down configuration (link size)

Hierarchy enumeration

Provides a complete PCI Express protocol hierarchy enumeration process including resource allocation

Skew Adding skew between lanes
Clock recovery Recover clock from bitstream or use reference clock
Clock jittering Add jitter to the clock
Ack\Nak Full control of the Ack\Nak protocol and timers, predefined sequence number, link CRC (LCRC), and duplicate TL error injections
Flow control credits Full control of Flow Control Credits (FCCs), including initial allocation of FCCs and the frequency of on-the-fly FCC updates
All interfaces Serial, 8-bit, 10-bit, PIPE 3.0, PIPE 4.0, PIE8
Support for all sidebands WAKE#, CLKREQ#, PERST#
Support for major devices End Point, Legacy End Point, Root Complex, Bridge, Switch, PHY-DUT
Complete modeling of four address spaces Memory, I\O, Configuration, MSI\MSI-X
Virtual channels Automatic, user-defined flow control initialization per virtual channel (VC)
Function level reset Full compliance

Interrupts

Handles interrupt mechanisms (MSI, MSI-X, INTx)

Power management

Provides full power management support (D-states, L-states, ASPM)

Supported Design-Under-Test Configurations

Root Complex End Point Switch/Bridge
Full Stack Controller Only PHY Only

Test Suite Options

Basic CMS PureSuite TripleCheck

 

 

Test Suite Comparison

 BasicCMSPureSuiteTripleCheck
Constrained-random example tests
Directed compliance tests
Constrained-random compliance tests
Tests targeting all protocol layers
3rd party simulator test execution
SystemVerilog functional coverage model
efunctional coverage model
Verification plan mapped to protocol specification
Verification plan integration with Cadence vManager metric-driven analysis system
Verification plan integration with 3rd party simulator environments

User Feedback

"When faced with the important decision as to which IP vendor has the most reputable and silicon-proven PCI Express IP, Denali (now Cadence) was the preferred vendor that met our critical high throughput and feature requirements. We rely on Cadence's high-quality, interoperable design and verification IP solutions, and excellent customer support to meet the PCIe 2.0 and IOV specifications, our product development timeframes, and achieve a competitive advantage. "
- Jim Finnegan, Sr. Vice President of Silicon Engineering, Netronome