Home: IP Portfolio > Verification IP > Simulation VIP > VIP for NVM Express 1.3

VIP for NVM Express 1.3

Specification Support

The Cadence® Verification IP (VIP) for NVMe 1.3 is part of Cadence's storage interface VIP portfolio. It provides a mature and highly capable compliance verification solution for the NVM Express (NVMe) protocol. It is applicable for IP, SoC, and system-level verification. The VIP is compatible with industry-standard Universal Verification Methodology (UVM), and runs on the Cadence Incisive Enterprise Simulator as well as on Synopsys VCS and Mentor Graphics Questa simulators.

The Cadence VIP for NVMe 1.3 seamlessly integrates with Cadence VIP for PCI Express® (PCIe®) for all generations (Gen 1.0, Gen 2.0, Gen 3.0, and Gen 4.0).  The Cadence VIP for NVMe 1.3 supports the NVMe Specification Revision 1.3, which can be downloaded at: http://www.nvmexpress.org/specifications.


Key Features



Admin Command Set Supports all of the mandatory Admin Command set, which defines the commands that can be submitted to the Admin Submission Queue.
NVM Command Set Supports all of the mandatory NVM command set. The NVM command set is a specification-defined I/O command set used with an I/O queue pair.
I/O Queue Configurable I/O submission/completion queues:
  • Up to 64K queues
  • Each queue supports up to 64K outstanding commands
Admin Queue Configurable Admin submission/completion queues
Controller-Level Reset CC.EN transitions from '1' to '0'
Subsystem-Level Reset Support for NVM Subsystem Reset
Command Arbitration Configurable command arbitration schemes:
  • Round robin
  • Weighted round robin
  • Vendor specific
Interrupt Support
  • Pin based
  • MSI (single and multiple message)
Multi-Path I/O Support for two or more completely independent PCIe paths between single host
Namespace Sharing Support for two or more hosts to access common shared namespace
Namespace Management Support of Namespace management command used to create/delete namespace
PRP Entry and List Supports physical region page (PRP) entry that points to physical memory page


Key Verification Capabilities

  • Standalone NVMe mode

Topologies Supported

VIP as NVMe Host (over PCIe)


VIP as NVMe Subsystem (over PCIe)


Test Suite Options

Basic CMS PureSuite TripleCheck


Test Suite Comparison

Constrained-random example tests
Directed compliance tests
Constrained-random compliance tests
Tests targeting all protocol layers
3rd party simulator test execution
SystemVerilog functional coverage model
efunctional coverage model
Verification plan mapped to protocol specification
Verification plan integration with Cadence vManager metric-driven analysis system
Verification plan integration with 3rd party simulator environments