Home: IP Portfolio > Verification IP > Simulation VIP > VIP for PCI Express 4.0

VIP for PCI Express 4.0

The Cadence® Verification IP (VIP) for PCI Express® (PCIe®) 4.0 supports a wide range of verification platforms, all major simulators and the industry-standard Universal Verification Methodology (UVM). The VIP core is written in native C for excellent performance, with seamless integration with all verification languages - SystemVerilog, e, Verilog, VHDL, and SystemC®.

In addition to all VIP for PCI Express 1.1 and 2.0 and VIP for PCI Express 3.0 have to offer, the VIP for PCI Express 4.0 adds Gen 4-related checks and controls.

Specification Support

The VIP is compliant with PCI Express specification 4.0 rev 1.0. The specification can be downloaded only by members of the PCI-SIG website: http://www.pcisig.com/home.


Key Features

Feature Name
Description

Device type

Root Complex, End Point, Legacy End Point, Switch, PHY DUT, Bridge

Interface

Serial, Parallel, PIPE 4.4

Link rate

Supports all PCI Express speeds, 2.5GT/s, 5.0GT/s, 8.0 GT/s, 16.0 GT/s
Link width

Configurable link width support x1, x2, x4, x8, x16, x32

Full support for up and down configuration

Virtual channel Automatic or user-defined flow control initialization per virtual channel
Side-band signal support WAKE#, CLKREQ#, PERST#
Protocol timers
  • Full configurability
  • ACK, NAK, Replay timer simplification for Gen 4.0
Fault Isolation Advanced error reporting (AER) to assist in fault isolation and root cause analysis
Equalization Perform and control equalization flow for all PCIe generations (Gen 1.0 to Gen 4.0)
Flow control credit (FCC)

Full control of flow control credits

  • Gen 4.0 support for flow control scaling
  • Initial allocation of FCCs
  • Dynamic FCC updates
Retimer Support Root complex and End Point support for recognizing retimer in the topology. Retimer Model (active and passive) not available
Tag Scaling 10-bit extended tag support to increase number of outstanding non-posted requests.
Rx Margining Lane margining at receiver for 16GT/s
Clock compensation Gen 4.0 updated SKP OS support
Elastic Buffer Mode Ability to control the elasticity buffer operating mode: Nominal Half Full/Nominal Empty
Electrical Idle Infer electrical idle condition for all PCIe generations (Gen 1.0 to Gen 4.0)
LTSSM

Complete link training status state machine (LTSSM) modeling

  • Configuration states
  • Power saving states
  • Recovery states
Skew Ability to insert skew between lanes
Clock Recovery

Clock recovery mechanisms supported

  1. Incoming bit stream
  2. Reference clock
Clock jitter Ability to add jitter to clock
Address space

Support for all types of address spaces

  • Memory
  • I\O
  • Configuration
  • MSI\MSI-X
Function Level Reset Full compliance
ECN support
  • PASID
  • PASID Translation 
  • Multicast
  • Latency Tolerance Reporting (LTR)
  • TLP Prefix
  • TLP Processing Hints
  • Optimized Buffer Flush/Fill
  • ASPM Optionality
  • Protocol Multiplexing (PMUX)
  • Separate Refclk Independent SSC Architecture (SRIS)
  • L1 PM substate with CLKREQ
  • Expanded Resizable BAR

Key Verification Capabilities

The capabilities below are additive to PCI Express 1.1 and 2.0 and PCI Express 3.0:

  • Operates at 16 GT/s
  • Multi-Lane Rx Error reporting per lane in the Lane Error Status register
  • Inferring of EI for 16 GT/s
  • Tag Scaling
  • Flow Control Scaling
  • Rx Margining

Key Features

FEATURE NAME
DESCRIPTION

Testbench language Interfaces

SystemVerilog, e, SystemC, Verilog, VHDL, c

UVM Agent

Yes

Trace Debug

Yes

Functional Coverage - e

Yes

Functional Coverage - SV

Yes

Compliance Management System

--

TripleCheck

Yes

Save & Restore (IES only)

Yes

Performance report

Yes

Accelerated VIP

Yes

Supported Design-Under-Test Configurations

Root Complex End Point Switch/Bridge
Full stack Controller-only PHY-only

 

Test Suite Options

Basic CMS PureSuite TripleCheck

 

Test Suite Comparison

 BasicCMSPureSuiteTripleCheck
Constrained-random example tests
Directed compliance tests
Constrained-random compliance tests
Tests targeting all protocol layers
3rd party simulator test execution
SystemVerilog functional coverage model
efunctional coverage model
Verification plan mapped to protocol specification
Verification plan integration with Cadence vManager metric-driven analysis system
Verification plan integration with 3rd party simulator environments