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VIP for TileLink

This Cadence® Verification IP (VIP) provides support for the TileLink specification. It provides a highly capable compliance verification solution simulation, making it applicable to intellectual property (IP), system-on-chip (SoC), and system-level verification. The VIP for TileLink runs on all leading simulators. It supports user interfaces in SV-UVM, plain SV, and C. The VIP includes a bus functional model (BFM) with automatic protocol checkers, supports random stimuli, and collects functional coverage.

The TileLink protocol is a standard of the RISC-V Foundation® designed for RISC-V processors. TileLink is a chip-scale interconnect standard providing multiple masters with coherent memory-mapped access to memory and other slave devices. TileLink is designed for use in a SoC to connect general-purpose multiprocessors, co-processors, accelerators, DMA engines, and simple or complex devices, using a fast scalable interconnect providing both low-latency and high-throughput transfers.

Specification Support

The Cadence VIP for TileLink protocol provides support for specification versions 1.7.1 and 1.8. The specifications are available at https://www.sifive.com/documentation.

Protocol Features

The VIP for TileLink verifies the design under test (DUT) by providing active slave and master agents for generating and driving stimuli. It provides passive slave and master agents for checking the protocol and collecting coverage. The VIP agents are highly configurable to support any combination of protocol configurations and optional features. The VIP is architected to enhance design verification productivity, ensure high-quality designs, and deliver maximum performance.

Product Highlights

The following table describes key features from the specification that are implemented in the VIP.

Feature Name

Description

TileLink Version 1.7.1

Channels A and D

Configurable option to use automatic slave responses

TL-UL

TL-UL conformance level, including Flow Control Rules, Deadlock Freedom, Request-Response message ordering, Errors, and Byte lanes

TL-UH

TL-UH conformance level, including Burst Messages and Atomic Operations

Reset

Drive, sample, and check the reset signal

Operations and Messages

Support the operations: PutFullData, PutPartialData, Get, ArithmeticData, LogicalData, Intention

TileLink Version 1.8

Channels A and D

Drive, sample, and check the signals and operations on channels A and D

TL-UL 

TL-UL conformance level, including Flow Control Rules, Deadlock Freedom, Request-Response message ordering, Errors, and Byte lanes

TL-UH

TL-UH conformance level, including Burst Messages and Atomic Operations

Reset

Drive, sample, and check the reset signal

Operations and Messages

Support the operations: PutFullData, PutPartialData, Get, ArithmeticData, LogicalData, Intention

Bus Errors

Drive, sample, and check the denied and corrupt signals

Key Verification Capabilities

  • Plugs into existing verification environments

  • Rapid test bench integration reduces time to first test

  • Accelerates protocol compliance verification

  • Models both Master and Slave

  • Includes both Active (Bus Functional Model) BFM and Passive (Monitor) agents

  • Active responder agent (Slave) supports four modes of response:

    • Auto-response: The responder has internal memory, and behaves like a memory, responding correctly to Write and Read operation initiated by the initiator agent. No user intervention is needed, though user can always override the default legal behavior.

    • Response from callback: The user must write a callback function implementation and fill the response fields once a request is received.

    • Response Out-Of-Order with a request queue: The user can wait in the test (for example, in the UVM sequence) for requests to be received into a provided request queue. Select any pending request, out of order if desired. Fill the response fields of the selected request, and send the response.

    • Response Out-Of-Order with automatic data response: Similar to the previous mode, only the Read data is filled from the internal memory of the Slave, and the user does not need to set the Response-Data field.

  • Memory consistency checking, in passive slave agent, which tracks the Writes and Reads to and from the slave DUT, and verifies that the DUT behaves like a perfect memory

  • Creates SOMA configuration for functionality and timing with the PureView tool:As an alternative to the SOMA-based configuration, the VIP also supports the SV-UVM config flow

    • Parameters defined in the TileLink specification, such as agent types, signal widths, and so forth
    • Parameters provided for ease of use and verification purpose such as slave response mode, and so forth
  • As an alternative to the SOMA-based configuration, the VIP also supports the SV-UVM config flow

  • Generates constrained-random transactions, with a full set of constraints in SystemVerilog user interface

  • Collects functional coverage of the protocol in the tested scenarios

  • Provides simulation-level configuration file, .denalirc, with keyword/value pairs to globally control the agents

  • Enables callback capabilities to support powerful and flexible user control over the sent and received transactions:

    • Transaction callbacks are triggered during the life-cycle of a transaction and can be used for error-injection or fine-granularity control of timing of bus signals
    • Memory/register callbacks are triggered whenever memory is accessed without polling
  • Provides control of the agent through flexible register interfaces:Provides powerful error injection capability to simulate how the DUT would react to real-world errors

    • Model-specific registers allow for real-time status and model simulation control such as behaviors, error severity, and so forth
  • Provides powerful error injection capability to simulate how the DUT would react to real-world errors

  • Handles error detection, reporting, logging, and complete checking of protocol rules

  • Language support: SystemVerilog and C language testbenches

  • Methodology support: Complies with the Universal Verification Methodology (UVM)

  • Simulator support: Cadence Xcellium Parallel Logic Simulation, IES, VCS, MTI

 

Other Supported Features

UVM Agent

Yes

Trace Debug

Yes

Assertion Coverage

No

Functional Coverage - SystemVerilog

Yes

RapidCheck

No

TripleCheck

No 

Transaction Log

No

Training, Documentation, and Usage Information