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VIP for TileLink

This Cadence® Verification IP (VIP) provides support for the TileLink specification. It provides a highly capable compliance verification solution simulation, making it applicable to intellectual property (IP), system-on-chip (SoC), and system-level verification. The VIP for TileLink runs on all leading simulators. It supports user interfaces in SV-UVM, plain SV, and C. The VIP includes a bus functional model (BFM) with automatic protocol checkers, supports random stimuli, and collects functional coverage. Cadence provides an integrated solution for interconnect verification that supports the verification of coherent interconnect and performance analysis that provides automated generation of testbenches. The VIP provides a framework for system-level coherency, integrated automatic protocol checks and coverage model.

The TileLink protocol is a standard of the RISC-V Foundation® designed for RISC-V processors. TileLink is a chip-scale interconnect standard providing multiple masters with coherent memory-mapped access to memory and other slave devices. TileLink is designed for use in a SoC to connect general-purpose multiprocessors, co-processors, accelerators, DMA engines, and simple or complex devices, using a fast-scalable interconnect providing both low-latency and high-throughput transfers.

Supported specification: 

The Cadence VIP for TileLink protocol provides support for specification versions 1.7.1 and 1.8.


  • Support testbench language interfaces for SystemVerilog, UVM, OVM, e and SystemC 
  • Generates constrained-random transactions and provides full control over all request and response messages
  • Dynamic activation support to enable the user to set the VIP as active or passive without changing the testbench while determining during run time which instance to instantiate
  • Callbacks access at various protocol events for transaction modification, scoreboarding and debugging
  • Packet tracker creation for easy debugging 
  • Support for error injection
  • Provides extensive coverage
  • Seamless integration with System Verification Scoreboard (SVD)


The following table describes key features from the specification that are implemented in the VIP.

Feature Name


Channels Drive, sample, and check the signals and operations on channels A and D for TL-UL/TL-UH conformance level and on channels A, B, C, D and E for TL-C conformance level 
TL-UL  Support for TL-UL conformance level including Flow Control Rules, Deadlock Freedom, Request-Response message ordering, Errors and Byte lanes
TL-UH Support for TL-UH conformance level including Burst Messages and Atomic Operations

Support for TL-C conformance level, including support for coherent caches

Operations and Messages Support all Operations and Messages 
Automatic Responses Support for Automatic Responses by the responder to respond correctly to Write and Read operation initiated by the initiator agent. No user intervention is needed, though user can always override the default legal behavior

Bus Errors

Drive, sample, and check the denied and corrupt signals


TileLink VIP comes along with a testsuite of scenarios for easy VIP evaluation and deployment 

Testsuite link: "Please contact us for further information" 

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