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VIP for PMBus

Incorporating the latest protocol updates, the Cadence® Verification IP (VIP) for PMBus provides a complete bus functional model (BFM), integrated automatic protocol checks, coverage model, and compliance tests. The VIP for PMBus is designed for easy integration in testbenches at IP, system-on-chip (SoC), and system levels, and helps to reduce time to test, accelerate verification closure, and ensure end-product quality. The VIP for PMBus runs on all major simulators and supports SystemVerilog verification language along with associated methodologies, including the Universal Verification Methodology (UVM) and Open Verification Methodology (OVM).

Specification Support

The VIP for PMBus supports the latest version of the PMBus specification.

  • PMBus Specification, version 1.3.1
    • Power System Management Protocol Specification Part I – General Requirements, Transport And Electrical Interface
    • Power System Management Protocol Specification Part II – Command Language

Product Highlights

The following table describes key features from the specification that are implemented in the VIP for PMBus.

Feature NameDescription

PMBus Devices

VIP configurable as master, slave, or host
PEC (Packet Error Checking) Performs PEC on transmit and receive data on applicable packets
Address Resolution Protocol Supports resolve addresses for devices on the bus
Device Timeout Supports device timeout condition detection
Command Protocol Supports all (Group,Extended,Zone read/write,Host Notify) command protocols with and without a packet error code
Clock Generation and Data Arbitration Supports clock generation using defined clock timings and data arbitration
Clock Synchronization Between Two Masters Supports clock synchronization when more than one master drives clock

Key Verification Capabilities

  • Compliance: Contains predefined checks to verify that the design under test (DUT) components and devices adhere to the protocol rules defined in the Protocol Specification.
  • Coverage: Monitors, checks, and collects coverage on bus traffic, transport protocols, and messages.
  • Random error injection promotes easy testing of scenarios.
  • Traffic:
    • Generates or emulates PMBus traffic. Can generate or emulate both master and slave traffic. Can also generate multi-agent driving.
    • Generates constrained-random bus traffic.
    • Responds to bus traffic as a slave.
  • Transaction tracker: Very comprehensive tracker file includes all the PMBus transactions with parsed information of all the fields monitored by the VIP for PMBus.

Other Supported Features

Testbench Language Interfaces SystemVerilog UVM
UVM Agent Yes
Trace Debug Yes
Functional Coverage - e No
Functional Coverage - SystemVerilog Yes
TripleCheck No

Supported Design-Under-Test Configurations

Initiator Target Expander


Test Suite Options

Basic CMS PureSuite TripleCheck

 

Test Suite Comparison

 BasicCMSPureSuiteTripleCheck
Constrained-random example tests
Directed compliance tests
Constrained-random compliance tests
Tests targeting all protocol layers
3rd party simulator test execution
SystemVerilog functional coverage model
efunctional coverage model
Verification plan mapped to protocol specification
Verification plan integration with Cadence vManager metric-driven analysis system
Verification plan integration with 3rd party simulator environments

Training