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VIP for I2S

The Cadence® Verification IP (VIP) for I2S library is a ready-made, highly configurable VIP for the I2S protocol. It allows tests to be run in a pure simulation environment. It provides a highly capable compliance verification solution that supports simulation, formal analysis, and hardware acceleration platforms, making it applicable to intellectual property (IP), system-on-chip (SoC), and system-level verification. The VIP for I2S is compatible with the industry-standard Universal Verification Methodology (UVM) and runs on all leading simulators.

Specification Support

The VIP for I2S is based on the following specifications:

  • I2S BFM Requirement Specification, Version 0.7 – 19 Sep 2012
  • I2S bus specification, Philips Semiconductors - 5 June 1996
  • Philips I2S Specification, version 1.1.

Product Highlights

Key Features

Feature Name
Description

Word Length Programmability 

Supports 8, 12, 16, 20, 24, 32, and user-defined

Configurability

Fully configurable VIP configuration: Master/Slave, Transmitter/Receiver, Active/Passive

Default transactions

Configurable default transactions

Functionality

Full I2S Transmitter and Receiver functionality, DSP Mode, Left Justified, and MultiChannel

Time Division Multiplexing (TDM)

Supports 2,4,8 Channel Multiplexing with Programmable Word Length

Full Duplex Mode

Supports TDM, DSP mode, Left Justified, Right Justified

Test Cases

Several test cases are included in the VIP

Key Verification Capabilities

  • Dynamic Activation Support: The user can set the VIP as active or passive without changing the testbench, and determine, during run time, which instance to instantiate.

Supported Interfaces

  • UVM SystemVerilog
  • SystemVerilog

Supported simulators

  • Xcelium
  • VCS
  • MTI