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VIP for Compute Express Link (CXL)

The Cadence® Verification IP (VIP) for Compute Express Link (CXL) is part of the Cadence family of VIP for PCI Express® (PCIe®).  Built on top of the PCIe 5.0 infrastructure, CXL is an open industry standard for high-bandwidth, low-latency interconnects. It defines the connectivity between the host processor and accelerators/memory devices and smart NICs.   

The VIP for CXL leverages Cadence's mature industry-leading VIP for PCIe. Built on top of an industry-known and -proven platform that was designed for easy integration in testbenches at the IP, system-on-chip (SoC), and system level, the VIP for CXL runs on all simulators and supports SystemVerilog along with the widely adopted Universal Verification Methodology (UVM). This enables verification teams to reduce time spent on environment development, and redirect the saved time to cover a larger verification space, accelerate verification closure, and ensure end-product quality.

With a layered architecture and powerful callback mechanism, verification engineers can verify CXL features at each functional layer (PHY, link, transport, and application layer) and create highly targeted designs while taking advantage of the latest design methodologies for random testing to cover a larger verification space.

 

 

Specification

The VIP is compliant with Compute Express Link Specification 2.0 revision 1.0.

The specification can be downloaded only by members of the Compute Express Link (CXL) Consortium from the website at https://www.computeexpresslink.org/.

Protocol Features

Important features offered in the Cadence VIP for CXL 1.1 are listed below

Feature Name
Description
New Feature
Device Configuration Host, Device  
Device Type

Type 1: Caching Devices/Accelerators

  • CXL.io
  • CXL.cache

Type 2: Accelerators with Memory

  • CXL.io
  • CXL.cache
  • CXL.mem

Type 3: Memory Buffers

  • CXL.io
  • CXL.mem
 
Protocol Support
  • CXL.io
  • CXL.mem
  • CXL.cache
 
Interface
  • Serial
  • PIPE 5.2
 
Link Rate
  • Native support: 32 GT/s
  • Downgraded support: 16GT/s and 8GT/s
 
Link Width
  • Native widths (x16, x8,x4)
  • Degraded widths (x2, x1)
 
Downstream Port Support
  • Root complex integrated endpoint (RCiEP) for CXL 1.1
  • EP for CXL 2.0
Updated
Register Space
  • Configuration space registers (CXL DVSEC)
  • Control status registers (CXL 2.0 DVSEC)
  • CXL RCRB base
Updated
FLIT Support
  • NULL flit
  • CXL.io transaction mapping in FLIT
  • CXL.mem/cache protocol FLIT
  • CXL.mem/cache control FLIT
    • RETRY
    • LLCRD
    • INIT
 
Flex Bus Support
  • Alternative Protocol Support
  • Framing and packet layout
  • Recovery.Idle
  • Config.Idle
  • Framing error handling
  • Physical Layer Latency Optimization (Sync Header Bypass)
Updated
Arb/MUX
  • vLSM 1.0 and 2.0
  • Weighted round-robin
  • Arbitration bypass mode
  • ALMP/vLSM bypass
Updated
Enumeration

Bypass enumeration

 
CXL.io
  • Configuration space registers
  • Memory-mapped registers
  • Memory type indication on ATS
  • PM messages, credits, and initialization
  • PM VDM
  • Deferrable Memory Write (DMWr) ECN
Updated
CXL.mem
  • M2S Req/RwD
  • S2M NDR/DRS
  • M2S Req/S2M NDR (cache-related)
  • Forward progressing rules
  • Speculative memory read
  • Memory error reporting
  • QoS telemetry
Updated
CXL.cache
  • D2H request/response
  • H2D request/response
  • Cache-ability details and request restriction
  • Biasing
Updated
Mem/Cache Link Layer
  • Initialization
  • Retry flow
  • ACK/LLCRD forcing
  • Remote Retry State Machine (RRSM)
  • Local Retry State Machine (LRSM)
  • Cache-side poison
Updated
Integrity and Data Encryption (IDE)
  • CXL.io encryption
  • CXL.mem/cache encryption
  • Authentication: DOE/SPDM/CMA
    • Discovery
    • Negotiation
    • Device attestation
    • Key negotiation
    • Bypass mode
    • Containment and Skid mode
  • Error handling
Update

 

Exceptions  

  • BIfurcation: Testbench solution

 

Key Verification Capabilities

  1. Enables verification of both host and device designs for all device types (Type 1-3)
  2. Bypass capabilities
    1. Enumeration bypass
    2. Arbitration bypass
    3. ALMP/vLSM bypass
    4. IDE authentication bypass
  3. Error injection via callbacks and common built-in scenarios
  4. Configurable Cache/Mem state modeling
    1. Auto-response (Cadence generic cache model)
    2. Message-only (User controlled cache state and LPC/memory modeling)
    3. Cache-mem core off

 

Other Supported Features

UVM Agent Yes
Trace Debug Yes
Functional Coverage - SystemVerilog Yes
TripleCheck Yes

 

 

Training, Documentation, and Usage Information

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