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UART Simulation Verification IP (VIP)

The Cadence® Verification IP (VIP) for UART provides a mature, highly capable compliance verification solution for the UART Protocol. The UART VIP supports the simulation platform, making it applicable to intellectual property (IP), system-on-chip (SoC), and system-level verification. The VIP is compatible with the industry-standard Universal Verification Methodology (UVM) and runs on all leading simulators.

The Universal Asynchronous Receiver/Transmitter (UART)  is a transmission protocol, which is omnipresent in the consumer electronics, PC, and mobile products. UART supports two kinds of devices: a transmitter sends 5-, 6-, 7-, or 8-bit characters over a TX channel, and a receiver detects and receives the characters on the RX channel.

Specification Support

The UART VIP supports the standard UART 16550 Specification, available at http://www.opencores.org.

Product Highlights

Key features implemented in the VIP are listed in the table below.

Feature NameDescription
Full-Duplex Support for full-duplex asynchronous communications 
Baud Rate
  • Baud rate generation subsystem
  • Auto baud rate generation
Data Word Length Programmable data word length (5, 6, 7, or 8 bits)
Stop Bits/Character 
  • Configurable stop bits (1 or 2 stop bits)
  • 1.5 stop bits for 5-bit character length
Error Detection Flags
  • Overrun error
  • Frame error
  • Parity error
Fully Prioritized Interrupt Sources
  • RX data available
  • TX holding register empty
  • RX line status interrupt
  • Modem status interrupt
TX/RX FIFOs Support for up to 128-byte transmit and receive FIFOs
Flow Control Support for hardware flow control using RTS/CTS signals
Asynchronous/Synchronous Mode Supports both UART and USART operations

Key Verification Capabilities

  • Compliance: Contains predefined checks to verify that the DUT agents adhere to the protocol rules defined in the UART specification
  • Coverage: Monitors, checks, and collects coverage on Baud Rate, Error Flags and Interrupt Sources
  • Built-in error injection mechanism
  • Random error injection promotes easy testing of scenarios

Other Supported Features

Functional CoverageSystemVerilog
Platforms Operates in simulated platform
Testbench Language Interfaces SystemVerilog, e

Supported Design-Under-Test Configurations

Transmitter Receiver Hub/Switch
Full Stack Controller Only PHY Only

Test Suite Options

Basic CMS PureSuite TripleCheck


Test Suite Comparison

Constrained-random example tests
Directed compliance tests
Constrained-random compliance tests
Tests targeting all protocol layers
3rd party simulator test execution
SystemVerilog functional coverage model
efunctional coverage model
Verification plan mapped to protocol specification
Verification plan integration with Cadence vManager metric-driven analysis system
Verification plan integration with 3rd party simulator environments