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The Cadence® VIP for SRIO provides support for the SRIO protocol specification. It provides a mature, highly capable compliance verification solution that supports simulation, protocol checking, coverage collection, and analysis, making it applicable to intellectual property (IP), system-on-chip (SoC), and system-level verification. The VIP for SRIO is compatible with the industry-standard Universal Verification Methodology (UVM) and runs on all leading simulators.

The RapidIO protocol is a simple and efficient interconnect designed specifically for high-speed embedded applications and appropriate to serve as a system-level fabric. By implementing protocol processing in hardware, many quality-of-service and flow-control mechanisms are an inherent part of the PHY, maximizing efficiency and throughput while minimizing latency and switch complexity. Backed by new data plane extensions that enable RapidIO switches to encapsulate virtually any data protocol, the RapidIO specification is an ideal interconnect technology, enabling developers to consolidate interconnect layers, as well as both control and data planes, into a single fabric, reducing cost while increasing overall system reliability.

The RapidIO standard is defined in three layers: logical, transport, and physical. The logical layer defines the overall protocol and packet formats. This is the information necessary for endpoints to initiate and complete a transaction. The transport layer provides the necessary route information for a packet to move from endpoint to endpoint. The physical layer describes the device-level interface specifics such as packet transport mechanisms, flow control, electrical characteristics, and low-level error management. This partitioning provides the flexibility to add new transaction types to the logical specification without requiring modification to the transport- or physical-layer specifications.


The VIP for SRIO supports SRIO Protocol versions 1.3, 2.0, and 2.1, 3.0 as defined in the SRIO Protocol Specification.

The specification is available at http://www.rapidio.org/rapidio-specifications/#tab1757.

Key Features

Feature Name

IO Logical

Input/Output packet formats are supported

Message Passing

Message passing architecture and packet formats are supported

Globally shared Memory

Globally shared distributed memory model architecture and packet formats are supported

Flow Control

Flow Control Logical Layer management based on source, destination and physical channel is supported

Data Streaming

Data Streaming Logical specification is supported


1x, 2x, 4x, 8x and 16x Lanes are supported


Both IDLE1 and IDLE2 sequences and therefore Short and Long Control Symbols are supported

VC support

Multiple virtual channels on PHY are supported


Both reliable and continuous traffic (RT and CT) are supported

Phy Flow Control

Both receiver-ended and transmitter-controlled flow control on Physical Layer are supported

EndPoint Device

EndPoint Device features are supported

Transport Large Device

Both small and large device IDs are supported

SRIO 3.0 Features

64b/67b Encoding

Support for 64b/67b encoding: codewords, ordered sequences, and IDLE3

Lane Speed

Support for 10.3125Gbaud lane speed

ackID Size

Increase ackID size for IDLE3 to 12 bits

Large Packets

Support for large packets, Dev32

Gbaud Links

Specific link initialization state machines to support initialization of 10.3125Gbaud links

Gbaud Links

Asymmetric operation of 10.3125Gbaud links

Multiple Packets

Allowed Packet Accepted control symbols to acknowledge multiple packets

Error Recovery

Input/output error recovery protocol updated in order to enable faster recovery

Per-Port Register Block Format

New per-port register block format, with new/modified registers

Time Synchronization

Added time synchronization support

Key Verification Capabilities

  • Compliance: Contains predefined checks to verify that the DUT agents (initiator and target) adhere to the protocol rules defined in the SRIO Protocol 2.1 Specification
  • Coverage: Monitors, checks, and collects coverage on bus traffic
  • Error injection: Optional
  • Traffic:
    • Generates or emulates SRIO traffic, can generate or emulate both initiator and target traffic
    • Generates constrained-random bus traffic
    • Responds to bus traffic as a target
  • Transaction tracker: Configurable tracking of all the transactions


The VIP for SRIO doesn't support Switch Device features

Other Supported Features

Testbench Language Interfaces

SystemVerilog and e

Simulator Support


UVM Agent


Functional Coverage - e


Compliance Management System


Training, Documentation, and Usage Information

See the Verification IP page on Cadence Online Support for product manuals, training, other documentation, and usage information.