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SRIO 3.0 Simulation Verification IP (VIP)

Specification Support

The SRIO 3.0 VIP supports SRIO Protocol versions 3.0 as defined in the SRIO Protocol Specification. 

The specification is available here: http://www.rapidio.org/rapidio-specifications/#tab1757

Key Features

Feature Name
Description

IO Logical

Input/Output packet formats are supported

Message Passing

Message passing architecture and packet formats are supported

Globally shared Memory

Globally shared distributed memory model architecture and packet formats are supported

Flow Control

Flow Control Logical Layer management based on source, destination and physical channel is supported

Data Streaming

Data Streaming Logical specification is supported

Multi-Lane

Currently, only 1x is supported

IDLE2

Both IDLE1 and IDLE2 sequences and therefore Short and Long Control Symbols are supported

VC support

Multiple virtual channels on PHY are supported

CT

Both reliable and continuous traffic (RT and CT) are supported

Phy Flow Control

Both receiver-ended and transmitter-controlled flow control on Physical Layer are supported

EndPoint Device

EndPoint Device features are supported

Transport Large Device

Both small and large device IDs are supported

SRIO 3.0 Features

64b/67b Encoding

Support for 64b/67b encoding: codewords, ordered sequences, and IDLE3

Lane Speed

Support for 10.3125 Gbaud lane speed

ackID Size

Increase ackID size for IDLE3 to 12 bits

Large Packets

Support for large packets, Dev32

Gbaud Links

Specific link initialization state machines to support initialization of 10.3125 Gbaud links

Gbaud Links

Asymmetric operation of 10.3125 Gbaud links

Multiple Packets

Allowed Packet Accepted control symbols to acknowledge multiple packets

Error Recovery

Input/output error recovery protocol updated in order to enable faster recovery

Per-port Register Block Format

New per-port register block format, with new/modified registers

Time Synchronization

Added time synchronization support

Supported Design-Under-Test Configurations

Host Device Hub/Switch
Full Stack Controller Only PHY Only

Test Suite Options

Basic CMS PureSuite TripleCheck

 

Test Suite Comparison

 BasicCMSPureSuiteTripleCheck
Constrained-random example tests
Directed compliance tests
Constrained-random compliance tests
Tests targeting all protocol layers
3rd party simulator test execution
SystemVerilog functional coverage model
efunctional coverage model
Verification plan mapped to protocol specification
Verification plan integration with Cadence vManager metric-driven analysis system
Verification plan integration with 3rd party simulator environments