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SPI Simulation Verification IP (VIP)

Specification Support

The SPI VIP supports the following specifications:

  • Samsung SPI based on the Exynos 5250 spec Revision 1.00
  • Motorola SPI based on Block Guide V03.06

Key Features

Feature Name

Full duplex

Simultaneous transfer from master and slave.

Variable size shift registers

Supports 8/16/32-bit shift register for Tx/Rx.

Variable bus sizes

Supports 8-bit/16-bit/32-bit bus interface.

Tx and Rx FIFOs

Supports two independent 32-bit wide transmit and receive FIFOs.

Master/Slave modes

Supports Master-mode and Slave-mode.

Rx only

Supports Receive-without-transmit operation.

Slave select output

Supports SS output.

Mode fault error

Supports mode fault error flag with CPU interrupt capability.

Clock polarity

Supports serial clock with programmable polarity and phase.

Control on wait mode

Supports control of SPI operation during wait mode.

Supported Design-Under-Test Configurations

Host Device Hub/Switch
Full Stack Controller Only PHY Only

Test Suite Options

Basic CMS PureSuite TripleCheck


Test Suite Comparison

Constrained-random example tests
Directed compliance tests
Constrained-random compliance tests
Tests targeting all protocol layers
3rd party simulator test execution
SystemVerilog functional coverage model
efunctional coverage model
Verification plan mapped to protocol specification
Verification plan integration with Cadence vManager metric-driven analysis system
Verification plan integration with 3rd party simulator environments