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SATA 6G Simulation Verification IP (VIP)

Specification Support

Cadence VIP for the SATA protocol provides support for SATA Specification version 3.1.

Product Highlights


Key Features

Feature Name
ACS -3 Many feature sets and commands from ACS commands are supported
ASR Asynchronous Signal Recovery
ATAPI commands ATA Packet Interface Support
Embedded port multiplier

Device behaves as if it has multiple memory subsystems to behave as port multiplier
Coherent read and write to different ports
Different feature configurations for each port (Eg. Port 0 ATA, Port 1 ATAPI)

Finite state machine (FSM) All finite state machines and state transition checks
Initialization Clock recovery and speed negotiation, OOB signaling with different OOB data, signature FIS, error injection and speed up of bypass initialization


Supports Serial 1 bit as well parallel 10/20/40-bit interface

Interface power states Partial, Slumber, Device Sleep
Memory subsystem System, Buffer, and Log memory
NCQ Native Command Queueing
FSM All the Finite state machines and state transition checks
Protocol checks Does protocol checks at each layer, such as physical, link, transport, and command
PIO and DMA engine Multiple PRD table implementation
Protocol checks Does protocol checks at each layer, such as physical, link, transport and command
Controllable protocol checkers and passive monitors 
Send/Receive FPDMA Queued Commands Send and Receive FPDMA Queued Commands
DMATp primitive Terminate a DMA data transmission

Supported Design-Under-Test Configurations

Host Device Port Multiplier
Full Stack Controller Only PHY Only

Test Suite Options

Basic CMS PureSuite TripleCheck


Test Suite Comparison

Constrained-random example tests
Directed compliance tests
Constrained-random compliance tests
Tests targeting all protocol layers
3rd party simulator test execution
SystemVerilog functional coverage model
efunctional coverage model
Verification plan mapped to protocol specification
Verification plan integration with Cadence vManager metric-driven analysis system
Verification plan integration with 3rd party simulator environments