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SAS 6G Simulation Verification IP (VIP)

Specification Support

SAS VIP supports SAS (Serial Attached SCSI) Specification SPL-2.

The specification is available at http://www.t10.org. This is an internal working document of T10, a Technical Committee of Accredited Standards Committee INCITS (International Committee for Information Technology Standards) and is available only for members of INCITS, its technical committees and their associated task groups.

Key Features

Feature Name
Description

Support for handling link layer errors in SSP transport layer.

Address frame arbitration Supports arbitration between multiple OPEN address frames.
Expander Support Supports basic expander functionality.
Frame Bursting Feature Supports Frame bursting for READ/WRITE commands.
INITIATOR and TARGET Supports verification of both INITIATOR and TARGET SAS device types
Interlocked and Non-interlocked transmission Supports frame transmission as per interlocked and non-interlocked frame type.
Link Connection Control Supports all LINK layer state machines for connection control, Transmitter, Receiver.
Link Flow Control Supports RRDY, CREDIT_BLOCKED etc primitives which are used for flow control.
Link Reset Sequence Supports PHY Reset Sequence, Hard Reset Sequence and Link Identification sequence.
Operating Modes Supports G1/G2/G3 speeds (1.5/3/6 Gbps).
PHY Reset Sequence Supports OOB sequence, Speed Negotiation Sequence.
PHY and LINK Timers Supports all PHY/LINK layer timers.
PHY Training Sequence

Supports PHY training sequence at 6 Gbps.

Rate Matching Feature Supports Link rate matching feature at 1.5/3/6 Gbps
SAS Frame Types Supports all frame types for INITIATOR and TARGET, that is, SSP_COMD, SSP_DATA, SSP_TASK, SSP_XFER, SSP_RESP.

SPL-3 Persistent-Connection

Support for SPL-3 Persistent-Connection feature
Transport Layer Protocols Supports SSP and SMP transport layer protocols.
Wide-port Support Supports wide-port of x2 and x4 (2/4 PHYs) configuration.

Supported Design-Under-Test Configurations

Initiator Target Expander
Full stack Controller-only PHY-only

 

Test Suite Options

Basic CMS PureSuite TripleCheck

 

Test Suite Comparison

 BasicCMSPureSuiteTripleCheck
Constrained-random example tests
Directed compliance tests
Constrained-random compliance tests
Tests targeting all protocol layers
3rd party simulator test execution
SystemVerilog functional coverage model
efunctional coverage model
Verification plan mapped to protocol specification
Verification plan integration with Cadence vManager metric-driven analysis system
Verification plan integration with 3rd party simulator environments