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SAS 12G Simulation Verification IP (VIP)

Specification Support

This VIP supports SAS (Serial Attached SCSI) Specification revision 11-036r9

Key Features

Feature Name
Address frame arbitration Supports arbitration between multiple OPEN address frames
BMC Encoding/Decoding Supports BMC encoding/decoding feature of PHY
Error TTIUs and Error Response TTIUs Supports transmission and reception of Error TTIUs and Error Response TTIUs
Frame Bursting Feature Supports Frame bursting for READ/WRITE commands
INITIATOR and TARGET Supports verification of both INITIATOR and TARGET SAS device types
Interlocked and non-interlocked transmission Supports frame transmission as per interlocked and non-interlocked frame type
Link connection control Supports all LINK layer state machines for connection control, transmitter, receiver
Link flow control Supports RRDY, CREDIT_BLOCKED etc primitives which are used for flow control
Link reset sequence Supports PHY reset sequence, hard reset sequence, and link identification sequence
Operating modes Supports G1/G2/G3/G4 speeds (1.5/3/6/12Gbps)
PHY and LINK timers Supports all PHY/LINK layer timers
PHY reset sequence Supports OOB sequence, Speed Negotiation Sequence
PHY training sequence

Supports PHY training sequence at 6Gbps

PHY transmitter/receiver training sequence Supports PHY transmitter/receiver training sequence at 12Gbps
Rate matching feature Supports link rate matching feature at 1.5/3/6/12Gbps
SAS frame types Supports all frame types for INITIATOR and TARGET: SSP_COMD, SSP_DATA, SSP_TASK, SSP_XFER, SSP_RESP

SPL-3 Persistent-Connection

Support for SPL-3 Persistent-Connection feature

Transport layer protocols Supports SSP and SMP transport layer protocols

Supported Design-Under-Test Configurations

Initiator Target Expander
Full Stack Controller Only PHY Only

Test Suite Options

Basic CMS PureSuite TripleCheck


Test Suite Comparison

Constrained-random example tests
Directed compliance tests
Constrained-random compliance tests
Tests targeting all protocol layers
3rd party simulator test execution
SystemVerilog functional coverage model
efunctional coverage model
Verification plan mapped to protocol specification
Verification plan integration with Cadence vManager metric-driven analysis system
Verification plan integration with 3rd party simulator environments