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PLB 6 Simulation Verification IP (VIP)

Specification Support

The specifications for PLB4 and PLB6 are IBM confidential. 

Key Features

Feature Name


Supports command, read data, and write data buses - DCR, PLB4, PLB6

Interface Supports master/slave/snooper pin, snoopable/non-snoopable commands - PLB4, PLB6
Address ordering Supports address overlapping read/write - PLB4, PLB6
Cache coherency Supports cache coherency for snoopers - PLB6
Data transfer Supports bytes, half-word, word, or line/burst transfer - PLB4, PLB6

Supported Design-Under-Test Configurations

Master Slave Hub/Switch
Full Stack Controller Only PHY Only

Test Suite Options

Basic CMS PureSuite TripleCheck


Test Suite Comparison

Constrained-random example tests
Directed compliance tests
Constrained-random compliance tests
Tests targeting all protocol layers
3rd party simulator test execution
SystemVerilog functional coverage model
efunctional coverage model
Verification plan mapped to protocol specification
Verification plan integration with Cadence vManager metric-driven analysis system
Verification plan integration with 3rd party simulator environments

User Feedback

"As the demand increases for interoperable and platform-independent Power Architecture solutions, Denali (now Cadence) has continually provided invaluable expertise in the toolkit development for the latest PLB specifications. IBM's collaboration with Cadence gives designers the ability to quickly implement customized Power Architecture based applications in world-leading semiconductor technologies."
- Michael Paczan, Chairman, Technical Committee, Power.org