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PHY VIP Solution

The Cadence® PHY Verification IP (VIP) family provides a mature, highly capable verification solution for verifying the PHY layer of complex protocols such as PCI Express® (PCIe®), MIPI® CSI-2, DSI, and DDR. The VIP support the simulation platforms and enable metric-driven verification of IP designs against various PHY protocol specifications. The VIP are compatible with the industry-standard Universal Verification Methodology (UVM) and support all leading simulators.

The PHY VIP solution is designed to address the unique challenges of PHY design verification that are often not addressed with higher layer VIP:

  • Built-in, end-to-end scoreboard to ensure the integrity of the data across the PHY-RX path and TX path, as well as loopback (where applicable)

  • Ability to send protocol-agnostic traffic, to easily test scenarios without the overhead of the higher protocol layers

  • Ability to connect to a protocol VIP to simulate protocol linkup and real protocol traffic

  • Enhanced support for SSC and jitter on the serial interface to stress receiver logic

  • Coverage on both serial and parallel interfaces

  • Latency checking on both TX and RX data paths

  • Includes a PHY monitor that ensures all actions on the parallel interface are properly propagated to the serial interface and vice versa

  • TripleCheck test suite, uniquely designed to address PHY specific scenarios with vPlan mapped to the relevant parallel interface specification

Specification Support

  • PIPE specification version 4.3, 4.4.1 and 5.2 supports PHY layer for PCIe (3/4/5), USB 3.x, USB4, SATA, and DP.

  • C-PHY specification versions 1.2 and 2.0 and D-PHY specification versions 1.2, 2.1 and 2.5

  • MIPI M-PHY version 2.0, 3.1 and 4.0

  • Latest DFI specification versions, supports protocols for DDR4, DDR5, LPDDR4, LPDDR4, HBM2/HBM3

Verification Topologies

  • PHY DUT Standalone Mode - Used for protocol-agnostic traffic

       

 

  • PHY DUT Integrated Mode - Used for protocol-aware traffic

 

Key Verification Capabilities

  • Active, passive configuration

  • Flexible error injection capability

  • Exhaustive cover items for each protocol layer

  • Ability to configure all timing parameters

Other Supported Features

Methodology support

Yes

Platforms

Yes

Testbench Language Interfaces

SystemVerilog

Functional Coverage - SystemVerilog

Yes

Trace Debug

Yes

UVM Agent

Yes

Training, Documentation, and Usage Information