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VIP for OCP

Description

The Cadence OCP Verification IP (VIP) provides a mature, highly capable compliance verification solution for the OCP Protocol. Used on multiple production designs, the OCP VIP is applicable for Intellectual Property (IP), System-on-Chip (SoC), and system-level verification. The VIP is compatible with the industry standard Universal Verification Methodology (UVM) and runs on all leading simulators.

The Open Core Protocol International Partnership (OCP-IP) defines a point-to-point interface between two communicating entities, such as IP cores and bus interface modules (bus wrappers). One entity acts as the master of the OCP instance and the other as the slave. Only the master can present commands and is the controlling entity. The slave responds to commands presented to it.

Specification

OCP VIP supports the OCP-IP Protocol v3.0 which is incremental to OCP-IP Protocol version 2.2 and 2.1.

The specification is developed by OCP-IP organization: http://www.ocpip.org and is available only for the licensed users.

Protocol Features

The following table describes key features from the specification that are implemented in the VIP.

Feature Name
Description
New Feature
Blocking and non-blocking flow control options Supports both the blocking and non-blocking flow control options for the requests.
Clock enable Supports the enable signal for clock.
Connect/Disconnect feature Supports Connect-Disconnect feature for both Master and Slave
Enhanced semantics for the write response enable Ensures that the WriteNonPost (WRNP)and WriteConditional(WRC) commands always have responses regardless of whether write response enable has been set in the interface configuration, as defined in the OCP 2.2 Specification.
Generating and driving bus traffic as an OCP master Emulates the full behavior of an unlimited number of OCP masters capable of generating all types of OCP transfers, according to OCP 2.2 Specification.
Multithreading and tagging Supports multiple thread ids and multiple tag IDs.
Out-of-order response Supports out-of-order responses.
Request interleaving Supports request interleaving. The interleaving depth is determined from the signal MAtomicLength.
Responding to bus traffic as an OCP slave Emulates the full behavior of an unlimited number of OCP slaves that respond to traffic over a bus, and generates all types of responses to a DUT master, according to OCP 2.2 Specification.
Synchronous and asynchronous reset Supports both synchronous and asynchronous reset. It also supports reset on the fly.

Key Verification Capabilities

  • Supports Interconnect Validator to verify non-coherent interconnects.
  • Supports RTL auto configurator utility for both e and SV.
  • Compliance Management System automates protocol compliance verification
  • Generates constrained-random bus traffic.
  • Responds to bus traffic as a slave.
  • Monitors, checks, and collects coverage on bus traffic and interconnect.
  • Collects and handles transaction history and also traces it for debugging its elements.
  • Logs the bus traffic for the purpose of debugging its elements and DUT devices.
  • Includes hundreds of assertions for formal compliance verification.
  • Supports transaction extension and error injection feature in UVM.

Other Supported Features

Testbench language interfaces SystemVerilog, e
Simulator support IES, VCS, and MTI
Methodology support Universal Verification Methodology (UVM), OVM, and VMM
UVM Agent Yes
Trace Debug Yes
Functional Coverage - e Yes
Functional Coverage - SV Yes
Compliance Management System Yes
Interconnect Validator Yes

Training, Documentation, and Usage Information

See the Verification IP Support Home