Home: IP Portfolio > Verification IP > Simulation VIP > JTAG Simulation VIP

JTAG Simulation Verification IP (VIP)

Specification Support

The JTAG VIP supports the JTAG Protocol v1.c from 2001 as defined in the JTAG Protocol Specification.

Key Features

Feature Name
Description

Multiple slaves

Supports multiple slaves. Parallel/serial configuration is supported.

Instructions

Supports all standard defined instructions

Clamp

Optional instruction CLAMP is supported

High Z

Optional instruction HIGHZ is supported

Extest

Optional instruction EXTEST is supported

Extest pulse

Ooptional instruction EXTEST_PULSE is supported (from 1149.6 standard)

Extest train

Optional instruction EXTEST_TRAIN is supported (from 1149.6 standard)

Instruction length

Instruction length is configurable

Instruction codes

Instruction codes is configurable

Supported Design-Under-Test Configurations

Master Slave Hub/Switch
Full Stack Controller Only PHY Only

Test Suite Options

Basic CMS PureSuite TripleCheck

 

Test Suite Comparison

 BasicCMSPureSuiteTripleCheck
Constrained-random example tests
Directed compliance tests
Constrained-random compliance tests
Tests targeting all protocol layers
3rd party simulator test execution
SystemVerilog functional coverage model
efunctional coverage model
Verification plan mapped to protocol specification
Verification plan integration with Cadence vManager metric-driven analysis system
Verification plan integration with 3rd party simulator environments