Home: IP Portfolio > Verification IP > Simulation VIP > I2C Simulation VIP

I2C Simulation Verification IP (VIP)

Product Highlights

Specification Support

The I2C VIP supports the I2C Protocol v1.0, v2.0, v2.1, v3.0, and v5.0 as defined in the I2C Protocol Specification. 

Key Features

Feature Name

Multiple agents

Supports both multi-mastering and any number of slaves

Arbitration Master arbitration is supported
Clock stretching Stretching of the SCL clock
7-bit/10-bit addressing Configurable option to use for slave addressing
General call Optional command support, configurable for each slave
Start byte Sending of optional start byte in transactions is available
Speed modes All speed modes are supported: Standard, Fast, Fast Plus and High Speed
Glitch handling Supports optional glitch handling
Slave response control Implements user control of slave response fields such as data, slave busy, slave sending NACK, etc.
Software reset Optional software reset command is supported
Device ID Optional command device ID is supported

Supported Design-Under-Test Configurations

Master Slave Hub/Switch
Full Stack Controller Only PHY Only

Test Suite Options

Basic CMS PureSuite TripleCheck


Test Suite Comparison

Constrained-random example tests
Directed compliance tests
Constrained-random compliance tests
Tests targeting all protocol layers
3rd party simulator test execution
SystemVerilog functional coverage model
efunctional coverage model
Verification plan mapped to protocol specification
Verification plan integration with Cadence vManager metric-driven analysis system
Verification plan integration with 3rd party simulator environments