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VIP for SAS 24G

Specification Support

The Cadence® Verification IP (VIP) for SAS 24G (SAS XT) is the newest member in Cadence’s broad storage interface verification IP (VIP) portfolio. Serial Attached SCSI (SAS) has been the interface of choice for mission-critical enterprise storage subsystems, with the next-generation SAS 24G addressing the transmission and storage of data growing at an exponential rate due to an increasingly connected world. 

As a part of Cadence’s datacenter and cloud solution, the VIP for SAS 24G delivers a comprehensive solution ahead of the 2017 SAS plug-festival, when it is anticipated that the first SAS 24G designs will be unveiled and tested for interoperability.    

Built on top of an industry-known and -proven platform that was designed for easy integration in testbenches at the IP, system-on-chip (SoC), and system level, the SAS-24G VIP runs on all simulators and supports SystemVerilog along with the widely adopted Universal Verification Methodology (UVM). This enables verification teams to reduce time spent on environment development, and redirect the saved time to cover a larger verification space, accelerate verification closure, and ensure end-product quality.

The Cadence SAS 24G VIP is a complete verification solution that includes a complete bus functional model (BFM), integrated protocol checks, coverage model, a rich set of error injection capabilities, and compliance tests. 

Supporting all previous SAS generation data rates (1.5G, 3G, 6G, and 12G) along with all application-level protocols (SSP, SMP, STP), the VIP for SAS 24G allows users to verify all SAS device configurations (initiator, target, and expander). With a layered architecture and powerful callback mechanism, verification engineers can verify SAS features at each functional layer (Phy, link, transport, and application layer) and create highly targeted designs while taking advantage of the latest design methodologies for random testing to cover a larger verification space. 


Key Features

Feature Name
Description

Device type

Initiator

Target

Expander

Operating modes

Supports all SAS speeds: 1.5, 3, 6, 12, 24Gb/s

DWORD mode: 12Gb/s and lower

Packet mode: 24Gb/s and greater

Interface support

Serial: DWORD and Packet mode

Parallel:

  • DWORD mode: 10 bit, 16 bit, 32 bit, 40 bit
  • Packet mode: 32 bit, 128 bit
Transport Layer Protocols

SSP

SMP

STP

Expander support
  • Configurable support for 2 to 128 external expander ports
  • Each port can operate at different speeds
  • ECM, ECR, BPP support
Narrow/Wide port support

Support for narrow and wide ports

  1. Narrow: One PHY in the port
  2. Wide: Greater than one PHY per port
PHY Power conditions Support of PHY low-power conditions and sequences
PHY reset sequences OOB sequence, speed negotiation sequence generation and verification at all data rates
Active PHY transmitter adjustment (APTA)

Support for APTA in packet mode

Persistent connection Supports persistent connection in SSP connection
Primitives Support for complete set of primitives (generation and verification)
Logical links Support for multiplexing of logical links
Broadcast Support for all broadcast types
Frame support Supports for all frames (generation and verification)
Bypass capabilities OOB, Speed Negotiation, Training, Scrambler

 

Topologies Supported

Key Verification Capabilities

  • Active, Passive configuration

  • Flexibile error injection capability Exhaustive cover items for each protocol layer

    • Callback instracture at each protocol layer enables user to define design-specific error injection scenarios
    • Predefined sequences enable users to create more common error injection scenarios
    • Multiple error injection support
  • Ability to configure all timing parameters defined within the specification

Other Supported Features


Testbench language Interfaces
SystemVerilog
UVM Agent Yes
Trace Debug Yes
Functional Coverage - SV Yes
RapidCheck Yes
TripleCheck Yes

Supported Design-Under-Test Configurations

Initiator Target Expander


Test Suite Options

Basic CMS PureSuite TripleCheck

 

Test Suite Comparison

 BasicCMSPureSuiteTripleCheck
Constrained-random example tests
Directed compliance tests
Constrained-random compliance tests
Tests targeting all protocol layers
3rd party simulator test execution
SystemVerilog functional coverage model
efunctional coverage model
Verification plan mapped to protocol specification
Verification plan integration with Cadence vManager metric-driven analysis system
Verification plan integration with 3rd party simulator environments