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VIP for RFFE 3.0

Cadence provides a mature and comprehensive Verification IP (VIP) for the MIPI® RF Front-End Control Interface (RFFEsm) protocol. Incorporating the latest protocol updates, the Cadence® VIP for RFFE provides a complete bus functional model (BFM), integrated automatic protocol checks, and coverage model. Designed for easy integration in testbenches at IP, system-on-chip (SoC), and system levels, the VIP for RFFE helps you reduce time to test, accelerate verification closure, and ensure end-product quality. The VIP runs on all major simulators and supports SystemVerilog and e verification languages along with associated methodologies, including the Universal Verification Methodology (UVM) and Open Verification Methodology (OVM).

Specification Support

The VIP for RFFE supports the following specifications:

Protocol Features

The following table describes key features from the specification that are implemented in the VIP.

Feature Name
Description

Topology

Supports multiple slaves and multiple masters topology

Packet Generation

Supports Command, Address, Data, and No Response Frame generation

Master side supports master write/read and also master context transfer write/read

Supports all RFFE commands

Device Address Types

Supports MID (Master ID), GSID (Group Slave ID), USID (Unique Slave ID), and BSID (Broadcast Slave ID) device addresses

Triggers

Supports all user-configurable triggers

Supports timed triggers and external triggers

Bus Park Cycle

Supports slave-initiated bus park, master-initiated bus park, and silent bus park cycle

SSC

Supports generation and detection of Sequence Start Condition (SSC)

Bus Ownership Transfer

Supports master ownership handover for multi-master topology

Modes

Supports normal mode and secondary mode

HSDR

Supports Half-Speed Data Response for read access

Programmable USID

Supports all three methods to program Unique Slave ID (USID)

Score Boarding

Compares read data with expected data based on none/any/many trigger(s) happening for that address

Error Injection

VIP can inject and detect parity errors in any frame (command, address/data), various errors can be injected and detected as well in master ownership transfer command

VIP can send invalid command frame

VIP can manipulate trigger supported register addresses from backdoor

Event Notification

VIP provides notification for command/address/data frames sent, timed trigger event occurred (for each trigger) and reset occurred

 

 Key Verification Capabilities

  • SystemVerilog coverage infrastructure for extendable coverage

  • Callback-based error injection capability for creation of illegal stimulus from the VIP

  • Monitor agent with analysis ports, which can be used for score-boarding purpose

  • Transaction tracker: Configurable tracking of all the transactions on the channels

Known Limitations

  • Implementation of interrupt mechanism for interrupt capable slave (from RFFE v2.1 removed from RFFE v3.0)

Other Supported Features

Feature Name
Description

Testbench Language Interfaces

SystemVerilog

UVM Methodology

Up to version 1.2

Trace Debug

Yes

Functional Coverage - e

No

Functional Coverage - SystemVerilog

Yes

Training, Documentation, and Usage Information