Home: IP Portfolio > Verification IP > Simulation VIP > VIP for MIPI SPMI


Cadence provides a mature and comprehensive Verification IP (VIP) for the MIPI® SPMIsm (System Power Management Interface) protocol. Incorporating the latest protocol updates, the Cadence® VIP for SPMI provides a complete bus functional model (BFM), integrated automatic protocol checks, and coverage model. Designed for easy integration in testbenches at IP, system-on-chip (SoC), and system levels, the VIP for SPMI helps you reduce time to test, accelerate verification closure, and ensure end-product quality. The VIP runs on all major simulators and supports SystemVerilog and e verification languages along with associated methodologies, including the Universal Verification Methodology (UVM) and Open Verification Methodology (OVM).

Specification Support

The VIP for SPMI supports the following specifications

Protocol Features

The following table describes key features from the specification that are implemented in the VIP.




Supports multiple slaves and multiple masters topology


Supports both High Speed and Low Speed device classes

Master Connection

Supports Master Connection by Detection of SSC (Sequence Start Condition), Detection o Bus Idle, Detection of Bus arbitration

Master Arbitration

Supports Master Priority and Secondary arbitration requests

Slave Types

Supports both RCS (Request Capable Slave) and NRCS (Non Request Capable Slave) slaves

Slave Arbitration

Supports A-bit and SR-bit slave arbitration requests

Packet Generation

Supports Command, Address, Data, and No Response Frame generation, supports all SPMI commands

Device Address Types

Supports MID (Master ID), GSID (Group Slave ID), USID (Unique Slave ID) device addresses


Supports ACK /NACK mechanism as per version 2.0 specification

Arbitration Generation

Capability to generate simultaneous Arbitration request Scenario

Error Injection

Supports injection/detection of errors for example parity errors/ noise spike at different arbitration level


Supports generation and detection of SSC (Sequence Start Condition)

Event Notificaiton

 Arbitration win/lost, error detection (e.g., noise spike detection, etc.) command/data/address frame sent, slave A/SR bit eligibility status, etc.


Key Verification Capabilities

  • SystemVerilog coverage infrastructure for extendable coverage

  • Callback-based error injection capability for creation of illegal stimulus from the VIP

  • Monitor agent with analysis ports which can be used for scoreboarding purpose

  • Transaction tracker: Configurable tracking of all the transactions on the channels


Other Supported Features

Testbench Language Interfaces


UVM Methodology

Up to version 1.2

Trace Debug


Functional Coverage - e


Functional Coverage - SystemVerilog



Supported Design-Under-Test Configurations

MAC PHY Hub/Switch
Full Stack Controller Only PHY Only

Test Suite Options

Basic CMS PureSuite TripleCheck


Test Suite Comparison

Constrained-random example tests
Directed compliance tests
Constrained-random compliance tests
Tests targeting all protocol layers
3rd party simulator test execution
SystemVerilog functional coverage model
efunctional coverage model
Verification plan mapped to protocol specification
Verification plan integration with Cadence vManager metric-driven analysis system
Verification plan integration with 3rd party simulator environments

Training, Documentation, and Usage Information