Home: IP Portfolio > Verification IP > Simulation VIP > VIP for MIPI D-PHY and C-PHY


Cadence provides a mature and comprehensive Verification IP (VIP) for the D-PHY/C-PHY protocol, which is part of the MIPI® family. Incorporating the latest protocol updates, the Cadence® VIP for D-PHY/C-PHY provides a complete bus functional model (BFM), integrated automatic protocol checks, and coverage model. Designed for easy integration in testbenches at IP, system-on-chip (SoC), and system levels, the VIP for D-PHY/C-PHY helps you reduce time to test, accelerate verification closure, and ensure end-product quality. The VIP runs on all major simulators and supports SystemVerilog and e verification languages along with associated methodologies, including the Universal Verification Methodology (UVM) and Open Verification Methodology (OVM).

Specification Support

The VIP supports the following specifications:

Protocol Features

The following table describes key features from the specification that are implemented in the VIP.

Feature Name


PHY Monitor

Built-in score-boarding between DpDn/PPI interface, it also monitors error signal interface 

Reports any detected error on any lane on DpDn interface and is not reflected on PPI interface

PHY Interfaces

Supports D-PHY 2.5 and C-PHY 2.0 with both PHY interfaces (DpDn and PPI)

Operation Mode

Supports Control, HighSpeed, and Escape in LP and ALP operating modes


Supports continuous and non-continuous operation mode for DPDN

Supports continuous TxWordClkHS and RxWordClkHS clock operation for PPI

PPI Data Bus Width

Supports 16- and 32-bit PPI data bus width over C-PHY

Supports 8-, 16-, and 32-bit PPI data bus width over D-PHY

Data Lanes

Supports one to eight D-PHY/C-PHY data lanes

Bi-Directional Data Lane Turnaround

Supports Control Mode and Fast Lane Turnaround  for D-PHY and C-PHY (Forward-to-Reverse direction or Reverse-to-Forward direction)

Ultra-Low Power Mode (ULPM)

Supports Ultra-Low Power mode (ULPM) on clock and data lanes


Supports all 4 trigger commands, including low-power data after trigger transmission and low-power data pause


Supports transmission and detection of HS-Idle state between two HS bursts for D-PHY

Skew Calibration

Supports Initial , Periodic, and Alternate Skew Calibration(PRBS9 generation) for D-PHY


Supports injection and detection of optional user-programmable sequence as part of the HS preamble for C-PHY

Sync Word

Supports driving and detecting multiple sync words and its different types within HS burst for C-PHY

Calibration Preamble

Supports driving and detection of all three different formats of Calibration Preamble in HS burst for C-PHY

Alternative Low Power

Supports transmission and detection of ALP mode and different ALP Control codes for C-PHY and D-PHY

Supports PHY initialization and its detection in ALP mode

Memory Callbacks for Event Notifications

Supports D-PHY and C-PHY (DpDn and PPI) event notifications (Trigger Detected, ESC Abort Detected, and so forth)

Error Injection

Supports injection of errors at PHY level, for example, ERRSOTHS and ERREOTSYNCHS

Preamble Sequence

Supports transmission and detection of Preamble sequence during Start Of Transmission (SOT) in D-PHY


Key Verification Capabilities

  • SV coverage infrastructure for extendable coverage

  • Callback-based error injection capability for creation of illegal stimulus from the VIP

  • Predefined protocol checkers to verify the compliance of the PHY layers of the DUT model to protocol requirements

  • Monitor agent with analysis ports, which can be used for score-boarding purpose

  • Transaction tracker: PHY monitor has transaction details of DPDN as well as PPI Interface


Other Supported Features

Testbench Language Interfaces

SystemVerilog, e 

UVM Methodology

Up to version 1.2

Trace Debug


Functional Coverage - SV




Training, Documentation, and Usage Information