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MIPI UniPro Simulation Verification IP (VIP)

Industry's First UniPro VIP

Incorporating the latest protocol updates, the mature and comprehensive Cadence® Verification IP (VIP) for the MIPI ® UniProsm 1.8 Protocol provides a complete bus functional model (BFM), integrated automatic protocol checks, coverage model, and compliance tests. Designed for easy integration in testbenches at IP, system-on-chip (SoC), and system levels, the VIP for UniPro 1.8 helps you reduce time to test, accelerate verification closure, and ensure end-product quality. Our VIP runs on all major simulators and supports SystemVerilog and e verification languages along with associated methodologies, including the Universal Verification Methodology (UVM) and Open Verification Methodology (OVM).

Specifications Support

The VIP for UniPro 1.8 supports the following MIPI UniPro specifications:

  • MIPI UniPro Specification, version 1.8

Protocol Features

The VIP for UniPro 1.8 verifies the design under test (DUT) by providing active slave and master agents for generating stimuli, and passive slave and master agents for checking the protocol and collecting coverage. 

Key Features

The following table describes key features from the specification that are implemented in the VIP for UniPro 1.8.

Feature Name
Description

Up to date specification

Supports MIPI UniPro 1.8, 1.61, 1.6, and 1.41 specification.

Serial and RMMI interfaces Supports Serial and RMMI interfaces (downstream).
CPort signal interface Supports CPort signal interface (upstream).
All layers supported Supports PHY Adapter, Data Link, Network, and Transport layers.
Built-in sequences PA link start up, (re-)initialization, configuration, and hibernate enter/exit sequences.
Data link layer Supports DLL initialization, TC0 and TC1, flow control, and acknowledgement mechanisms.

Transport layer

Supports TL connection management and addressing, segmentation and reassembly, 
end-to-end flow control, and multi-CPort arbitration.
Lane capabilities Supports up to four lanes, PWM G1-G7, HS G1-G4 on each direction, and A/B HS rate series.
Connectivity capabilities Supports testing of 1.6, 1.61, and 1.8 connection compatibility.

Key Verification Capabilities

  • Compliance: Contains predefined checks to verify that the DUT agents (master and slave) adhere to the protocol rules defined in the UniPro  Protocol 1.8,  UniPro Protocol 1.61, and UniPro Protocol 1.6 specifications.

  • Dynamic Activation Support: The user can set the VIP as active or passive without changing the testbench, and determine, during run time, which instance to instantiate.

  • Coverage: Monitors, checks, and collects coverage on bus traffic and interconnect.

  • Error Detection: Supports error detection on all layers, more than 200 different protocol checks.
  • Coverage: Monitors, checks, and collects coverage on bus traffic using hundreds of automatic protocol checks, including configuration and runtime checks.

  • Error Injection: Random and pre-defined error injections promote easy testing of scenarios and scenario creations.

  • Environment Setup: Configurable environment layers allow for early and specified verification of Data Link Layer.

  • Traffic: Transaction tracker: Configurable tracking of all the transactions on the channels.

    • Generates or emulates UniPro traffic. Can generate or emulate both master and slave traffic.

    • Generates constrained-random bus traffic.

Other Supported Features

Feature Name
Description

Testbench language interfaces

SystemVerilog and  e

Methodology

UVM, up to version 1.2

OVM

Trace debug

Yes

Functional coverage -  e

Yes

Functional coverage - SV

Yes

Compliance management system

No

TripleCheck

Yes

Simulator Support IES, VCS, and MTI

 

Supported Design-Under-Test Configurations

Master Slave Hub/Switch
Full Stack Controller Only PHY Only

Test Suite Options

Basic CMS PureSuite TripleCheck

 

Test Suite Comparison

 BasicCMSPureSuiteTripleCheck
Constrained-random example tests
Directed compliance tests
Constrained-random compliance tests
Tests targeting all protocol layers
3rd party simulator test execution
SystemVerilog functional coverage model
efunctional coverage model
Verification plan mapped to protocol specification
Verification plan integration with Cadence vManager metric-driven analysis system
Verification plan integration with 3rd party simulator environments