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MIPI SoundWire Simulation Verification IP (VIP)

The Cadence® Verification IP (VIP) for the MIPI® SoundWiresm Protocol provides a bus functional model (BFM), integrated automatic protocol checks and coverage model. It supports active or passive master, monitor and a configurable number of slaves (1-11).

The VIP for SoundWire runs on all major simulators (Cadence Incisive® Enterprise Simulator, as well as third-party simulators), and supports SystemVerilog and everification languages along with associated methodologies, including the Universal Verification Methodology (UVM) and Open Verification Methodology (OVM). It supports integration and traffic generation in all popular verification environments.

Specification Support

The VIP for SoundWire complies with the following MIPI SoundWire specifications:

  • Version 1.0, officially released by MIPI in February, 2015.
  • Version 1.1, officially released by MIPI in June, 2016

The latest specifications are available here: www.mipi.org

Product Highlights

  • First to market with SoundWire VIP support
  • Enables emulation with up to 11 slaves, with 1 to 14 data ports per slave
  • Supports Initialization sequence and enumeration process
  • Supports multi-lane configuration

Protocol Features

The following table describes key features from the specification that are implemented in the VIP for SoundWire.

Feature Name
Description
Bank switching Frame size and DP channels can be switched during activity.
Bulk payload Slave and Master devices support Bulk Payload Transport Protocol.
Command ownership Monitor can take command ownership from Master.
Data payload traffic Slave and Master devices can send data payload traffic.
Dynamic slave devices Dynamic addition and removal of Slave devices.
Enumeration Master assigns Dev_num for each newly attached slave.
Error scenarios Master and Slave can generate error scenarios.
Flow control Slave and Master devices can send asynchronous data payload traffic.
Full, reduced, and simplified data ports Support in Full, Reduced, and Simplified Data Ports.
High-PHY mode High-performance PHY.
Interrupts

Slave VIP replies automatically when interrupt needs to be generated based on configuration.

Limited WordLength Support in a limited set of values of the WordLength field.
Master PHY test modes Master device supports PHY test modes.
Multi-lane payload transport Up to 8 data lanes are supported.
Multicast and broadcast slave accesses Master can access slave registers through broadcast and multicast.
Resets Ability to perform all kinds of resets on the fly.
Slave command responses Slave VIP automatically replies with appropriate command responses.
Synchronization Sync slave with master SoundWire frame.
Test data modes Support of static and PRBS data payload sending.

Other Supported Features

Feature Name
Description

Testbench language interfaces

SystemVerilog and e

Methodology

UVM, up to version 1.2

OVM

Trace debug

Yes

Functional coverage - e

Yes

Functional coverage - SV

Yes

Compliance management system

No

TripleCheck

Yes

Interconnect validator

No
Simulator support IUS, VCS, and MTI
RapidCheck Yes

Key Verification Capabilities

  • Compliance: Contains predefined checks to verify that the DUT adheres to the protocol rules defined in the SoundWire specification.
  • Dynamic Activation Support: The user can set the VIP as active or passive without changing the testbench, and determine, during run time, which instance to instantiate.
  • Easy debugging: Advanced debugging trackers of the frame and data payload

Supported Design-Under-Test Configurations

Master Slave Monitor
Full Stack Controller Only PHY Only

Test Suite Options

Basic CMS PureSuite TripleCheck

Test Suite Comparison

 BasicCMSPureSuiteTripleCheck
Constrained-random example tests
Directed compliance tests
Constrained-random compliance tests
Tests targeting all protocol layers
3rd party simulator test execution
SystemVerilog functional coverage model
efunctional coverage model
Verification plan mapped to protocol specification
Verification plan integration with Cadence vManager metric-driven analysis system
Verification plan integration with 3rd party simulator environments