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MIPI M-PHY Simulation Verification IP (VIP)

Incorporating the latest protocol updates, the mature, highly capable Cadence® Verification IP (VIP) for the MIPI® M-PHYsm Protocol provides a complete bus functional model (BFM), integrated automatic protocol checks, coverage model, and compliance tests. It includes highly configurable and flexible simulation models of all the protocol layers, devices, and transaction types.

Designed for easy integration in testbenches at IP, system-on-chip (SoC), and system levels, the VIP for M-PHY helps you reduce time to test, accelerate verification closure, and ensure end-product quality. Our VIP runs on all major simulators (Cadence Incisive® Enterprise Simulator, as well as third-party simulators) and supports SystemVerilog and e verification languages along with associated methodologies, including the Universal Verification Methodology (UVM) and Open Verification Methodology (OVM). It supports integration and traffic generation in all popular verification environments.

Specification Support

The VIP for M-PHY supports the MIPI M-PHY specification version 4.1 and below.

The latest specifications are available here: 

Protocol Features

The following table describes key features from the specification that are implemented in the VIP. 

Feature Name
Description
Specification compliance Complies with MIPI M-PHY 4.1 specification.
Multi-lane Supports distribution and merging data over one to four lanes. Also supports a different number of lanes per 
sub-link (direction).
M-PHY Type 1 and Type 2 Supports Type 1 and Type 2.
M-PHY transmission modes
  • Supports multiple transmission modes with different bit-signaling and clocking schemes.
  • Supports multiple transmission speed ranges (PWM G1-G7, all Hs-GEARs) and rates per BURST mode.
M-PHY modes Supports Burst state, ACTIVATED SAVE states (SLEEP and STALL), and hibernate (“HIBERN8”) state.
M-PHY interface Supports serial interface (DpDn) and signaling interface (RMMI).

Key Verification Capabilities

  • Compliance: Contains predefined checks to verify that the DUT adheres to the protocol rules defined in the M-PHY Specification.
  • Dynamic Activation Support: The user can set the VIP as active or passive without changing the testbench, and determine, during run time, which instance to instantiate.
  • Error Detection: Supports error detection on all layers, more than 200 different protocol checks.
  • Coverage: Monitors, checks, and collects coverage on bus traffic and interconnect using hundreds of automatic protocol checks, including configuration and runtime checks.
  • Error Injection: Random and pre-defined error injections promote easy testing of scenarios and scenario creations.

 Other Supported Features

Feature Name
Description
Testbench language interfaces
SystemVerilog and e
Methodology
UVM and OVM
Trace debug
Yes
Functional coverage - e
Yes
Functional coverage - SV
Yes
Compliance management system
 -
TripleCheck
-
Interconnect validator
 -
Simulator support
IES, VCS, and MTI

Supported Design-Under-Test Configurations

Master Slave Hub/Switch
Full Stack Controller Only PHY Only

Test Suite Options

Basic CMS PureSuite TripleCheck

 

Test Suite Comparison

 BasicCMSPureSuiteTripleCheck
Constrained-random example tests
Directed compliance tests
Constrained-random compliance tests
Tests targeting all protocol layers
3rd party simulator test execution
SystemVerilog functional coverage model
efunctional coverage model
Verification plan mapped to protocol specification
Verification plan integration with Cadence vManager metric-driven analysis system
Verification plan integration with 3rd party simulator environments

User Feedback

"Mobile device users demand ever-increasing power-efficiency, and the MIPI Alliance chip-to-chip interfaces are an essential low-power technology for smartphone and tablet developers. As an early contributing member of the MIPI Alliance, Cadence has helped speed the adoption of mobile specifications, now including the M-PHY-based M-PCIe."
– Joel Huloux, Chairman of the Board, MIPI Alliance