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MIPI M-PHY Simulation Verification IP (VIP)

Incorporating the latest protocol updates, the mature, highly capable Cadence® Verification IP (VIP) for the MIPI® M-PHYsm Protocol provides a complete bus functional model (BFM), integrated automatic protocol checks, coverage model, and compliance tests. It includes highly configurable and flexible simulation models of all the protocol layers, devices, and transaction types.

Designed for easy integration in testbenches at IP, system-on-chip (SoC), and system levels, the VIP for M-PHY helps you reduce time to test, accelerate verification closure, and ensure end-product quality. Our VIP runs on all major simulators and supports SystemVerilog and e verification languages along with associated methodologies, including the Universal Verification Methodology (UVM) and Open Verification Methodology (OVM). It supports integration and traffic generation in all popular verification environments.

Specification

The VIP for M-PHY supports the MIPI M-PHY specification version 4.1 and below.

The latest specifications are available here: 

Protocol Features

The following table describes key features from the specification that are implemented in the VIP. 

Feature Name
Description
Specification Compliance Complies with MIPI M-PHY 4.1 and 5.0 specification

M-PHY Type 1 and Type 2

Supports Type 1 and Type 2

M-PHY Interface

Supports serial interface (DpDn) and signaling interface (RMMI)

M-PHY Modes

Supports Burst state, ACTIVATED SAVE states (SLEEP and STALL), and hibernate (“HIBERN8”) state
M-PHY Transmission Modes

Supports multiple transmission modes with different bit-signaling and clocking schemes

Supports multiple transmission speed ranges (PWM G1-G7, HS G1 - HS G5) and rates per BURST mode

Multi-Lane

Supports distribution and merging data over one to four lanes, also supports a different number of lanes per
sub-link (direction)

Test Mode Support for test mode functionality including loop-back mode

Key Verification Capabilities

  • Compliance: Contains predefined checks to verify that the DUT adheres to the protocol rules defined in the M-PHY Specification.
  • Dynamic Activation Support: The user can set the VIP as active or passive without changing the testbench, and determine, during run time, which instance to instantiate.
  • Error Detection: Supports error detection on all layers, more than 200+ different protocol checks.
  • Coverage: Monitors, checks, and collects coverage on bus traffic and interconnect using hundreds of automatic protocol checks, including configuration and runtime checks.
  • Error Injection: Random and pre-defined error injections promote easy testing of scenarios and scenario creations.

 

Supported Design-Under-Test Configurations

Master Slave Hub/Switch
Full Stack Controller Only PHY Only

 

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User Feedback

"Mobile device users demand ever-increasing power-efficiency, and the MIPI Alliance chip-to-chip interfaces are an essential low-power technology for smartphone and tablet developers. As an early contributing member of the MIPI Alliance, Cadence has helped speed the adoption of mobile specifications, now including the M-PHY-based M-PCIe."
– Joel Huloux, Chairman of the Board, MIPI Alliance