Home: IP Portfolio > Verification IP > Simulation VIP > MIPI I3C Simulation VIP

MIPI I3C Simulation Verification IP (VIP)

The Cadence® Verification IP (VIP) for MIPI® I3Csm VIP provides support for the MIPI I3C protocol specification. It provides a mature, highly capable compliance verification solution that supports simulation, protocol checking, coverage collection, and analysis, making it applicable to intellectual property (IP), system-on-chip (SoC), and system-level verification. VIP for I3C is compatible with the industry-standard Universal Verification Methodology (UVM) and runs on all leading simulators.

The I3C Specification describes the I3C interface (Improved Inter Integrated Circuit), which is used for easing sensor system design architectures by providing a fast, low-cost, low-power, two-wire digital interface for sensors.

The I3C Specification includes the following protocols:

  • Support for most Legacy I2C slave devices
  • Single Data Rate (SDR) – I2C protocol with I3C enhancements, running up to 12.9MHz
  • High Data Rate (HDR) – Additional modes that add significant functionality, but do not follow I2C protocol:
    • HDR-Dual Data Rate Mode (HDR-DDR)
    • HDR-Ternary Symbol Legacy Mode (HDR-TSL)
    • HDR-Ternary Symbol Pure-Bus Mode (HDR-TSP)

Specification Support

The I3C VIP complies with MIPI I3C specification version 1.0.

Protocol Features

Cadence MIPI I3C VIP verifies the design under test (DUT) by providing active slave and master agents for generating stimuli, and passive slave and master agents for checking the protocol and collecting coverage.

The following table describes key features from the specification that are implemented in the VIP.

Feature Name
Description
Dynamic address assignment Supports the mandatory dynamic address assignment mode including SETDASA.
I3C SDR mode SDR private read/write data transfers.
I3C CCC Mandatory and optional CCCs: Direct and broadcast commands.
Secondary master Supports processing Secondary Master mastership requests.
In-band interrupt Supports processing of in-band Interrupts from I3C slaves.
I3C HDR-DDR mode HDR-DDR enter and exit patterns, command coding, bus turnaround and error detection.
Arbitration Supports I3C address arbitration.
Hot Join Supports Hot-join procedure for adding slaves to the bus on the fly.
SDR Error Detection and Recovery Supports SDR Error Detection and Recovery Methods for I3C Master and I3C Slave Devices
I3C HDR-Ternary modes Supports HDR-TSP and HDR-TSL modes.
Slave response control Implements user control of slave response fields such as data, slave busy, slave sending NACK, etc.
I2C 50 ns glitch filter Supports optional 50 ns glitch filter for I2C devices.
I2C Clock Stretching Supports I2C Stretching.
I2C start byte Sending of optional start byte in transactions is available.
I2C speed modes Standard, Fast, Fast Plus, Ultra Fast and High Speed
I2C 7-bit/10-bit addressing Configurable option to use for slave addressing.
I2C Multi master Supports I2C Multi master feature

Key Verification Capabilities

  • Compliance: Contains predefined checks to verify that the DUT agents (master and slave) adhere to the supported protocol features. Defined in the MIPI I3C Protocol Specification.
  • Coverage: Monitors, checks, and collects coverage on bus traffic.
  • Error injection: Provides ability to generate intentionally erroneous traffic on the bus.
  • Supports any number of I3C and I2C slaves up to the limit of the specification.
  • Support I2C only mode to simulate the I2C protocol as defined in the I2C specification.
  • Traffic:
    • Generates or emulates I3C traffic. Can generate or emulate both master and slave traffic. Can also generate multi-agent driving.
    • Generates constrained-random bus traffic.
    • Responds to bus traffic as a slave.

Other Supported Features

Feature Name
Description

Testbench language interfaces

SystemVerilog  and e

Simulator support IES, VCS, and MTI
Methodology support Unified Verification Methodology (UVM), OVM

Trace Debug

Yes

Functional Coverage - SV

Yes

Supported Design-Under-Test Configurations

Master Slave Full Stack
PHY Only Controller Only

Test Suite Options

Basic CMS PureSuite TripleCheck

 

Test Suite Comparison

 BasicCMSPureSuiteTripleCheck
Constrained-random example tests
Directed compliance tests
Constrained-random compliance tests
Tests targeting all protocol layers
3rd party simulator test execution
SystemVerilog functional coverage model
efunctional coverage model
Verification plan mapped to protocol specification
Verification plan integration with Cadence vManager metric-driven analysis system
Verification plan integration with 3rd party simulator environments