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MIPI DSI Simulation Verification IP (VIP)

Incorporating the latest protocol updates, the mature and comprehensive Cadence® Verification IP (VIP) for the MIPI® Display Serial Interface (DSIsm) provides a complete bus functional model (BFM), integrated automatic protocol checks, coverage model, and compliance tests. Designed for easy integration in testbenches at IP, system-on-chip (SoC), and system levels, the VIP for DSI helps you reduce time to test, accelerate verification closure, and ensure end-product quality. Our VIP for DSI runs on all major simulators and supports SystemVerilog and e verification languages along with associated methodologies, including the Universal Verification Methodology (UVM) and Open Verification Methodology (OVM).


The VIP for DSI supports the following MIPI specifications:

See also:

Protocol Features

Key features from the spec that are implemented in the DSI VIP are listed below. 

Feature Name

Receiver and transmitter verification

Verifies both DSI processor and peripheral.

Physical layer

Includes the VIP for MIPI D-PHYsm for physical layer verification.
PHY interfaces Supports both PHY interfaces (DpDn and PPI).

Data lanes

Supports one to four data lanes.
Power state Supports both High-Speed and Low Power data transmission.

LP capabilities

Supports Ultra-Low Power mode (ULPM), triggers, and LP data transmission.
Transmission of multiple packets Supports several merged packets in a single PHY transmission.
Traffic modes

Supports sending and receiving of DSI packets and frames in command mode and all video modes.

Accurate video mode timing Supports both generation and checks of accurate video mode timings.

Control of payload data

Enables the user to control the frame and packet payload.
Read/write frame from/to file Enables the user to read a frame to or from a .ppm file.
Control packet data during BLLP period Enables the user to control the packets that are sent during BLLP periods in non-VACT lines.
VESA Display Stream Compression support Performs actual compression/decompression and provides a set of checkers for monitoring DSC-related traffic.
DSI packets tracker Creates a detailed log of observed DSI packets for efficient debug.

 Key Verification Capabilities

  • Compliance Management System automates protocol compliance verification
  • Dynamic Activation Support: The user can set the VIP as active or passive without changing the testbench, and determine, during run time, which instance to instantiate
  • Generates constrained-random bus traffic
  • Provides extensive coverage, verification plan, and test suite

  • Complies with the Unified Verification Methodology (UVM, OVM)
  • UVM configuration
  • Provides predefined error injection

  • Responds to bus traffic as a slave
  • Supports SystemVerilog and e language testbenches

Other Supported Features

Feature Name

Testbench Language Interfaces

SystemVerilog and e

UVM Methodology

Up to version 1.2

Trace Debug


Functional Coverage - e


Functional Coverage - SV


Simulator Support IES, VCS, and MTI

DPI Product Features

Key features from the spec that are implemented in the VIP for MIPI DPIsm are listed below.

Feature Name

Transmitter and receiver

Drives or monitors all possible frames.

Physical layer

Supports all color coding (16/18/24 bits and configuration 1,2,3).

Timing parameters

Supports all frames timing parameters.

DBI Product Features

Key features from the spec that are implemented in the VIP for MIPI DBIsm are listed below.

Feature Name

Transmitter and receiver

Drives or monitors all commands from Display Command Set (DCS).

PHY interfaces


  • Supports type A configuration (8,9,16 bits of data bus width).
  • Supports type B configuration (8,9,16 bits of data bus width).
  • Supports type C Option 2 and 3 configurations.

Physical layer

Supports all signals timing per interface configuration.


Supports variety of callbacks for better control and monitor functions.
Configuration/data Supports protocol checks of signal timings.

Supported Design-Under-Test Configurations

Transmitter Receiver Hub/Switch
Full Stack Controller Only PHY Only

Test Suite Options

Basic CMS PureSuite TripleCheck


Test Suite Comparison

Constrained-random example tests
Directed compliance tests
Constrained-random compliance tests
Tests targeting all protocol layers
3rd party simulator test execution
SystemVerilog functional coverage model
efunctional coverage model
Verification plan mapped to protocol specification
Verification plan integration with Cadence vManager metric-driven analysis system
Verification plan integration with 3rd party simulator environments