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VIP for MIPI Display Serial Interface 2 (includes C-PHY, D-PHY, DBI, and DPI)

Overview

Cadence provides a mature and comprehensive Verification IP (VIP) for the DSI-2sm protocol, which is part of the MIPI® family. Incorporating the latest protocol updates, the mature and comprehensive Cadence® VIP for DSI-2sm Protocols provides a complete bus functional model (BFM), integrated automatic protocol checks, coverage model, and compliance tests. Designed for easy integration in testbenches at IP, system-on-chip (SoC), and system levels, the VIP for DSI-2 helps you reduce time to test, accelerate verification closure, and ensure end-product quality. Our VIP runs on all major simulators and supports SystemVerilog and e verification languages along with associated methodologies, including the Universal Verification Methodology (UVM) and Open Verification Methodology (OVM).

Supported Specification: 

The VIP for DSI-2 supports the MIPI specifications for the DSI v1.3.1,  DSI2 v1.0, v1.1, DSI2 v2.0 and DPHY v1.2, v2.0, v2.1 and CPHY v1.1 and v1.



Product Highlights

  • Compliance Management System automates protocol compliance verification
  • Dynamic Activation Support: The user can set the VIP as active or passive without changing the testbench, and determine, during run time, which instance to instantiate
  • Generates constrained-random bus traffic
  • Provides SV extensive coverage, verification plan, and test suite
  • Complies with the Unified Verification Methodology (UVM, OVM)
  • UVM configuration: The user can configure the VIP agent using the UVM config class
  • Provides predefined error injection
  • Responds to bus traffic as a slave
  • Supports SystemVerilog and e language testbenches

Key Features

Key features from the specification that are implemented in the VIP for DSI-2 are listed below.

Feature Name

Description

Receiver and Transmitter Verification

Verifies both DSI processor and peripheral

Physical Layer

Includes the MIPI D-PHYsm/C-PHYsm VIP for physical layer verification
PHY Interfaces Supports both PHY interfaces (serial and parallel interfaces)

Data Lanes

Supports one to four data lanes
Power State Supports both High-Speed and Low Power data transmission

LP Capabilities

Supports Ultra-Low Power mode (ULPM), triggers and LP data transmission
Transmission of Multiple Packets Supports several merged packets in a single PHY transmission
Traffic Modes

Supports sending and receiving of DSI packets and frames in command mode and all video modes

Accurate Video Mode Timing Supports both generation and checks of accurate video mode timings
Control of Payload Data Enables the user to control the frame and packet payload
Scrambling Enables data scrambling in order to mitigate the effects of EMI and RF self-interference
Built-In Test Supports PRBS test debug pattern for C-PHY
Control Packet Data During BLLP Period Enables the user to control the packets that are sent during BLLP periods in non-VACT lines
VESA Display Stream Compression Support Performs actual compression/decompression and provides a set of checkers for monitoring of DSC-related traffic
Variable PPI HS Data Bus Width

Supports 8-, 16-, and 32-bit PPI HS data bus widths over D-PHY 2.0

Supports 16 and 32 PPI HS data bus widths over C-PHY

DSI2 v 1.1 Supports D-PHY specification 2.1 and C-PHY specification 1.2
DSI2 Over D-PHY 2.1 Supports HS-Idle State, Alternate Calibration, and Preamble sequence
DSI2 Over C-PHY 1.2 Supports ALP transactions and calibration sequence
DSI Packets Tracker Creates a detailed log of observed DSI packets for efficient debug
Video Frame for BTA and ULP during BLLP Supports sending and receiving BTA/ULP within video frame blanking period
DSI2 v2.0 Data Types

Supports data types SEP and PENP from Processor to Peripheral and vice versa and video frame data type PKT_PIXEL_STREAM_20_YCBCR422

Video Command Mode Seamless Transactions Enables VIP to change command to video and video to command mode based on DCS command

 

Simulation Testsuite 

Extensive testsuite, coverage model and verification plan with clear linkage to the specification for simple and fast compliance testing 

Testsuite Link: TripleCheck Test Suite

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