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MIPI DSI-2 Simulation Verification IP (VIP)

Incorporating the latest protocol updates, the mature and comprehensive Cadence®  Verification IP (VIP) for MIPI® DSI-2sm Protocols provides a complete bus functional model (BFM), integrated automatic protocol checks, coverage model, and compliance tests. Designed for easy integration in testbenches at IP, system-on-chip (SoC), and system levels, the VIP for DSI-2 helps you reduce time to test, accelerate verification closure, and ensure end-product quality. Our VIP for DSI-2 runs on all major simulators and supports SystemVerilog and e verification languages along with associated methodologies, including the Universal Verification Methodology (UVM) and Open Verification Methodology (OVM).

Specification Support

The DSI-2 VIP supports the following MIPI specifications:

Protocol Features

Key features from the specification that are implemented in the VIP are listed below.

Feature Name
Description

Receiver and transmitter verification

Verifies both DSI processor and peripheral.

Physical layer

Includes the MIPI D-PHY/C-PHY VIP for physical layer verification.
PHY interfaces Supports both PHY interfaces (DpDn and PPI).

Data lanes

Supports one to four data lanes.
Power state Supports both High-Speed and Low Power data transmission.

LP capabilities

Supports Ultra-Low Power mode (ULPM), triggers and LP data transmission.
Transmission of multiple packets Supports several merged packets in a single PHY transmission.
Traffic modes

Supports sending and receiving of DSI packets and frames in command mode and all video modes.

Accurate Video Mode Timing Supports both generation and checks of accurate video mode timings.
Control of payload data Enables the user to control the frame and packet payload.
Scrambling Enables data scrambling in order to mitigate the effects of EMI and RF self-interference.
Control packet data during BLLP period Enable the user to control the packets that are sent during BLLP periods in non-VACT lines.
VESA Display Stream Compression Support Performs actual compression/decompression and provides set of checkers for monitoring of DSC-related traffic.
Variable PPI HS Data Bus width Supports 8, 16 and 32 bit PPI HS data bus widths over D-PHY 2.0. Supports 16 and 32 PPI HS data bus widths over C-PHY.
DSI Packets Tracker Creates a detailed log of observed DSI Packets

 Key Verification Capabilities

  • Compliance Management System automates protocol compliance verification.

  • Dynamic Activation Support: The user can set the VIP as active or passive without changing the testbench, and determine, during run time, which instance to instantiate.

  • Generates constrained-random bus traffic.

  • Provides extensive coverage, verification plan, and test suite.

  • Complies with the Unified Verification Methodology (UVM, OVM).

  • UVM configuration: The user can configure the VIP agent using the UVM config class.

  • Provides predefined error injection.

  • Responds to bus traffic as a slave.

  • Supports SystemVerilog and e language testbenches.

Other Supported Features

Feature Name
Description

Testbench Language Interfaces

SystemVerilog and e

UVM Methodology

Up to version 1.2

Trace Debug

Yes

Functional Coverage - e

Yes

Functional Coverage - SV

Yes

Simulator Support IES, VCS, and MTI

DPI Product Features

Key features from the specification that are implemented in the VIP for DPIsm are listed below.

Feature Name
Description

Transmitter and receiver

Drives or monitors all possible frames.

Physical layer

Supports all color coding (16/18/24 bits and configuration 1, 2, 3).

Timing parameters

Supports all frame timing parameters.
UVM configuration The user can configure the VIP agent using the UVM config class.
Dynamic activation support The user can set the VIP as active or passive without changing the testbench, and determine, during run time, which instance to instantiate.

 DBI Product Features

Key features from the specification that are implemented in the VIP for DBIsm are listed below.

Feature Name
Description
Transmitter and receiver Drives or monitors all commands from the Display Command Set (DCS).
PHY interfaces
  • Supports type A configuration (8,9,16 bits of data bus width)
  • Supports type B configuration (8,9,16 bits of data bus width)
  • Supports type C option

Physical layer

Supports all signals timing per interface configuration.
Data Supports a variety of callbacks for better control and monitor functions.
Configuration/data Supports protocol checks of signal timings.
UVM configuration The user can configure the VIP agent using the UVM config class.
Dynamic activation support The user can set the VIP as active or passive without changing the testbench, and determine, during run time, which instance to instantiate.

Supported Design-Under-Test Configurations

Transmitter Receiver Hub/Switch
Full Stack Controller Only PHY Only

Test Suite Options

Basic CMS PureSuite TripleCheck

 

Test Suite Comparison

 BasicCMSPureSuiteTripleCheck
Constrained-random example tests
Directed compliance tests
Constrained-random compliance tests
Tests targeting all protocol layers
3rd party simulator test execution
SystemVerilog functional coverage model
efunctional coverage model
Verification plan mapped to protocol specification
Verification plan integration with Cadence vManager metric-driven analysis system
Verification plan integration with 3rd party simulator environments