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VIP for MIPI Display Serial Interface 2 (includes C-PHY, D-PHY, DBI, and DPI)

Incorporating the latest protocol updates, the mature and comprehensive Cadence® Verification IP (VIP) for MIPI® DSI-2sm Protocols provides a complete bus functional model (BFM), integrated automatic protocol checks, coverage model, and compliance tests. Designed for easy integration in testbenches at IP, system-on-chip (SoC), and system levels, the VIP for DSI-2 helps you reduce time to test, accelerate verification closure, and ensure end-product quality. Our VIP for DSI-2 runs on all major simulators and supports SystemVerilog and e verification languages along with associated methodologies, including the Universal Verification Methodology (UVM) and Open Verification Methodology (OVM).

Specification Support

The VIP for DSI-2 supports the following MIPI specifications:

Protocol Features

Key features from the specification that are implemented in the VIP for DSI-2 are listed below.

Feature Name
Description

Receiver and Transmitter Verification

Verifies both DSI processor and peripheral

Physical Layer

Includes the MIPI D-PHYsm/C-PHYsm VIP for physical layer verification

PHY Interfaces

Supports both PHY interfaces (DpDn and PPI)

Data Lanes

Supports one to four data lanes

Power State

Supports both High-Speed and Low Power data transmission

LP Capabilities

Supports Ultra-Low Power mode (ULPM), triggers and LP data transmission

Transmission of Multiple Packets

Supports several merged packets in a single PHY transmission

Traffic Modes

Supports sending and receiving of DSI packets and frames in command mode and all video modes

Accurate Video Mode Timing

Supports both generation and checks of accurate video mode timings

Control of Payload Data

Enables the user to control the frame and packet payload

Scrambling

Enables data scrambling in order to mitigate the effects of EMI and RF self-interference

Built-In Test

Supports PRBS test debug pattern for C-PHY

Control Packet Data During BLLP Period

Enables the user to control the packets that are sent during BLLP periods in non-VACT lines

VESA Display Stream Compression Support

Performs actual compression/decompression and provides a set of checkers for monitoring of DSC-related traffic

Variable PPI HS Data Bus Width

Supports 8-, 16-, and 32-bit PPI HS data bus widths over D-PHY 2.0

Supports 16 and 32 PPI HS data bus widths over C-PHY

DSI2 v 1.1

Supports D-PHY specification 2.1 and C-PHY specification 1.2

DSI2 Over D-PHY 2.1

Supports HS-Idle State, Alternate Calibration, and Preamble sequence

DSI2 Over C-PHY 1.2

Supports ALP transactions and calibration sequence

DSI Packets Tracker

Creates a detailed log of observed DSI packets for efficient debug

 

Key Verification Capabilities

  • Compliance Management System automates protocol compliance verification

  • Dynamic Activation Support: The user can set the VIP as active or passive without changing the testbench, and determine, during run time, which instance to instantiate

  • Generates constrained-random bus traffic

  • Provides extensive coverage, verification plan, and test suite

  • Complies with the Unified Verification Methodology (UVM, OVM)

  • UVM configuration: The user can configure the VIP agent using the UVM config class

  • Provides predefined error injection

  • Responds to bus traffic as a slave

  • Supports SystemVerilog and e language testbenches

Other Supported Features

Testbench Language Interfaces

SystemVerilog and e 

UVM Methodology

Up to version 1.2

Trace Debug

Yes

Functional Coverage - e

Yes

Functional Coverage - SystemVerilog

Yes

Simulator Support

IES, VCS, and MTI

The following features are not supported by the VIP:

  • Interlaced video mode

  • Section 8.7.2 of DSI spec version 1.2 - Frame Synchronized Transactions (not relevant for VIP)

DPI Product Features

Key features from the specification that are implemented in the VIP for DPIsm are listed below.

FEATURE NAME
DESCRIPTION

Transmitter and Receiver

Drives or monitors all possible frames

Physical Layer

Supports all color coding (16/18/24 bits and configuration 1, 2, 3)

Timing Parameters

Supports all frame timing parameters

UVM Configuration

The user can configure the VIP agent using the UVM config class

Dynamic Activation Support

The user can set the VIP as active or passive without changing the testbench, and determine, during run time, which instance to instantiate

The following features are not supported by the DPI VIP:

  • Driving the SD and CM signals
  • Largest frame supports up to 500,000 pixels

DBI Product Features

Key features from the specification that are implemented in the VIP for DBIsm are listed below.

FEATURE NAME
DESCRIPTION

Transmitter and Receiver

Drives or monitors all commands from the Display Command Set (DCS)

PHY Interfaces

Supports type A configuration (8,9,16 bits of data bus width)

Supports type B configuration (8,9,16 bits of data bus width)

Supports type C option

Physical Layer

Supports all signals timing per interface configuration

Data

Supports a variety of callbacks for better control and monitor functions

Configuration/Data

Supports protocol checks of signal timings

UVM Configuration

The user can configure the VIP agent using the UVM config class

Dynamic Activation Support

The user can set the VIP as active or passive without changing the testbench, and determine, during run time, which instance to instantiate

The following features are not supported by the DBI VIP:

  • Driving the TE signal

Test Suite Comparison

 BasicCMSPureSuiteTripleCheck
Constrained-random example tests
Directed compliance tests
Constrained-random compliance tests
Tests targeting all protocol layers
3rd party simulator test execution
SystemVerilog functional coverage model
efunctional coverage model
Verification plan mapped to protocol specification
Verification plan integration with Cadence vManager metric-driven analysis system
Verification plan integration with 3rd party simulator environments